公开(公告)号：US20230362408A1

公开(公告)日：2023-11-09

申请号：US18224143

申请日：2023-07-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH

IPC: H04N19/593 ,  H04N19/44 ,  H04N19/176

CPC classification number: H04N19/593 ,  H04N19/44 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: prohibits a first splitting method when arrangement and shapes of blocks obtained by splitting a first block multiple times by the first splitting method are identical to arrangement and shapes of blocks obtained by splitting the first block multiple times by a second splitting method different from the first splitting method, and when scan order of the blocks obtained by the first splitting method is identical to scan order of the blocks obtained by the second splitting method; and encodes the first block.

公开(公告)号：US20230362368A1

公开(公告)日：2023-11-09

申请号：US18343393

申请日：2023-06-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Ru Ling LIAO ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/50 ,  H04N19/60

CPC classification number: H04N19/119 ,  H04N19/176 ,  H04N19/50 ,  H04N19/60

Abstract: An encoder according to one aspect of the present disclosure encodes a block of an image, and includes a processor and memory connected to the processor. Using the memory, the processor partitions a block into a plurality of sub blocks and encodes a sub block included in the plurality of sub blocks in an encoding process including at least a transform process or a prediction process. The block is partitioned using a multiple partition including at least three odd-numbered child nodes and each of a width and a height of each of the plurality of sub blocks is a power of two.

公开(公告)号：US20230328248A1

公开(公告)日：2023-10-12

申请号：US18334176

申请日：2023-06-13

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/126 ,  H04N19/176 ,  H04N19/18 ,  H04N19/60 ,  H04N19/30 ,  H04N19/124

CPC classification number: H04N19/126 ,  H04N19/176 ,  H04N19/124 ,  H04N19/60 ,  H04N19/30 ,  H04N19/18

Abstract: Various embodiments provide an encoder that performs an up-conversion and a down-conversion on a first quantization matrix to generate a second quantization matrix, and quantizes transform coefficients of a current block using the second quantization matrix. The first quantization matrix has a first number of rows and a first number of columns equal to the first number of rows, and the second quantization matrix has a second number of rows and a second number of columns different from the second number of rows. In the up-conversion, the circuitry generates the second quantization matrix such that one of the second number of rows or the second number of columns is larger than the first number of rows. In the down-conversion, the circuitry generates the second quantization matrix such that the other of the second number of rows or the second number of columns is smaller than the first number of rows.

公开(公告)号：US20230319300A1

公开(公告)日：2023-10-05

申请号：US18331800

申请日：2023-06-08

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Sughosh Pavan SHASHIDHAR ,  Ru Ling LIAO ,  Hai Wei SUN ,  Han Boon TEO ,  Jing Ya LI ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Takahiro NISHI

IPC: H04N19/44 ,  H04N19/119 ,  H04N19/137 ,  H04N19/159 ,  H04N19/176

CPC classification number: H04N19/44 ,  H04N19/119 ,  H04N19/137 ,  H04N19/159 ,  H04N19/176

Abstract: An image decoder has circuitry coupled to a memory. The circuitry splits a current image block into a plurality of partitions. The circuitry predicts a first motion vector from a set of uni-prediction motion vector candidates for a first partition of the plurality of partitions, and decodes the first partition using the first motion vector.

公开(公告)号：US20230300366A1

公开(公告)日：2023-09-21

申请号：US18200782

申请日：2023-05-23

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/186

CPC classification number: H04N19/52 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: stores MV information and correction processing information into a FIFO buffer for an HMVP mode in association, the MV information being derived for a processed block and correction processing information being related to correction processing of a prediction image of the processed block; registers, in a prediction candidate list for a merge mode, one or more prediction candidates each being a combination of MV information and correction processing information, the prediction candidates including a prediction candidate which is a combination of the motion vector information and the correction processing information stored in the FIFO buffer; and selects a prediction candidate from the prediction candidate list when a current block is to be processed in the merge mode, and performs correction processing of a prediction image of the current block, based on the correction processing information.

公开(公告)号：US20230283771A1

公开(公告)日：2023-09-07

申请号：US18196763

申请日：2023-05-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: derives, as a first parameter, a total sum of absolute values of sums of horizontal gradient values respectively for pairs of relative pixel positions; derives, as a second parameter, a total sum of absolute values of sums of vertical gradient values respectively for the pairs of relative pixel positions; derives, as a third parameter, a total sum of horizontal-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fourth parameter, a total sum of vertical-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fifth parameter, a total sum of vertical-related sums of horizontal gradient values respectively for the pairs of relative pixel positions; and generates a prediction image to be used to encode the current block using the first, second, third, fourth, and fifth parameters.

公开(公告)号：US20230269390A1

公开(公告)日：2023-08-24

申请号：US18137042

申请日：2023-04-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Ryuichi KANOH

IPC: H04N19/513 ,  H04N19/176 ,  H04N19/182 ,  H04N19/196

CPC classification number: H04N19/513 ,  H04N19/176 ,  H04N19/182 ,  H04N19/196

Abstract: An encoder is an encoder that encodes a block in a picture using a prediction image of the block, and includes circuitry and memory. Using the memory, the circuitry: calculates a first average pixel value which is an average pixel value of first reference samples out of the first reference samples and second reference samples, The first reference samples are referable and located outside the block and adjacent to a first side of the block. The second reference samples are referable and located outside the block and adjacent to a second side of the block. When generating the prediction image, the circuitry applies the same prediction pixel value to inner samples among current samples to be processed that are included in the block. The inner samples constitute a quadrilateral region including at least two current samples in each of a horizontal direction and a vertical direction.

公开(公告)号：US20230247198A1

公开(公告)日：2023-08-03

申请号：US18296272

申请日：2023-04-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/117 ,  H04N19/14 ,  H04N19/159 ,  H04N19/174

CPC classification number: H04N19/117 ,  H04N19/14 ,  H04N19/159 ,  H04N19/174

Abstract: An encoder includes processing circuitry and a memory coupled to the processing circuitry. The processing circuitry is configured to: select a filter based at least on a prediction mode used for a first block, the filter including first filter coefficients for the first block and second filter coefficients for a second block; multiply values of first pixels among the first block and second pixels among the second block by the first filter coefficients to change a value of a first pixel in the first pixels; and multiply the values of the first pixels among the first block and the second pixels among the second block by the second filter coefficients to change a value of a second pixel in the second pixels.

公开(公告)号：US20230138357A1

公开(公告)日：2023-05-04

申请号：US18090621

申请日：2022-12-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Ryuichi KANOH

IPC: H04N19/31 ,  H04N19/117 ,  H04N19/172

Abstract: An encoder which encodes a video including a plurality of pictures includes circuitry and memory. Using the memory, the circuitry performs: encoding a first picture among the plurality of pictures; and performing (i) a first operation for encoding a parameter set for a second picture which follows the first picture in coding order among the plurality of pictures after encoding the first picture, and encoding the second picture after encoding the parameter set, or (ii) a second operation for encoding the second picture without encoding the parameter set after encoding the first picture. The circuitry performs the first operation when the second picture is a determined picture, in the performing of the first operation or the second operation.

公开(公告)号：US20230093946A1

公开(公告)日：2023-03-30

申请号：US18062455

申请日：2022-12-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/117 ,  H04N19/136 ,  H04N19/82 ,  H04N19/176 ,  H04N19/182 ,  H04N19/61 ,  H04N19/159

Abstract: A decoder includes a memory and processing circuitry. The processing circuitry, in operation, changes values of pixels in a first block and a second block to filter a boundary therebetween, using clipping such that change amounts of the respective values are within respective clip widths. The clip widths for the pixels in the first block and the second block are selected based on block sizes of the first block and the second block. The pixels in the first block include a first pixel located at a first position, and the pixels in the second block include a second pixel located at a second position corresponding to the first position with respect to the boundary. The clip widths include a first clip width and a second clip width corresponding to the first pixel and the second pixel, respectively, and the first clip width is different from the second width.