公开(公告)号：US20240340441A1

公开(公告)日：2024-10-10

申请号：US18748771

申请日：2024-06-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi Hashimoto ,  Kiyofumi Abe ,  Tadamasa Toma ,  Takahiro Nishi ,  Ryuichi Kanoh

IPC: H04N19/52 ,  H04N19/159 ,  H04N19/182

CPC classification number: H04N19/52 ,  H04N19/159 ,  H04N19/182

Abstract: An encoder includes: circuitry; and memory, in which using the memory, the circuitry, in affine motion compensation prediction in inter prediction for a current block, places a limit on a range within which motion estimation or motion compensation is performed, and performs the motion compensation for the current block.

公开(公告)号：US12114004B2

公开(公告)日：2024-10-08

申请号：US18065513

申请日：2022-12-13

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/51 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/51 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.

公开(公告)号：US20240323444A1

公开(公告)日：2024-09-26

申请号：US18675858

申请日：2024-05-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hai Wei SUN ,  Chong Soon Lim ,  Han Boon Teo ,  Jing Ya Li ,  Che Wei Kuo ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/70 ,  H04N19/124 ,  H04N19/132 ,  H04N19/186 ,  H04N19/80

CPC classification number: H04N19/70 ,  H04N19/124 ,  H04N19/132 ,  H04N19/186 ,  H04N19/80

Abstract: An encoder: includes circuitry, and memory coupled to the circuitry; stores a first parameter into a bitstream, the first parameter indicating whether a syntax element related to a chroma tool offset is present in the bitstream; when the first parameter indicates that the syntax element is present in the bitstream, (i) stores, in the bitstream, one or more second parameters that are used in deblocking filtering for a chroma sample of a current image, in addition to the syntax element, (ii) performs the deblocking filtering using the one or more second parameters, and (iii) encodes the current image; and when the first parameter indicates that the syntax element is not present in the bitstream, encodes the current image without storing the one or more second parameters into the bitstream.

公开(公告)号：US20240314296A1

公开(公告)日：2024-09-19

申请号：US18675704

申请日：2024-05-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

Abstract: Provided is an encoder includes: circuitry; and memory coupled to the circuitry, in which in operation, the circuitry: generates a prediction image of a current block to be processed, using a first motion vector; and updates a history based motion vector predictor (HMVP) table using a first candidate having the first motion vector, the HMVP table storing, in a first in first out (FIFO) method, a plurality of second candidates each having a second motion vector used for a processed block, and in the updating of the HMVP table, the circuitry: determines whether a size of the current block is less than or equal to a threshold size; and skips the updating of the HMVP table when the size of the current block is determined to be less than or equal to the threshold size.

公开(公告)号：US12081793B2

公开(公告)日：2024-09-03

申请号：US18226952

申请日：2023-07-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/52 ,  H04N19/137 ,  H04N19/186 ,  H04N19/176

CPC classification number: H04N19/52 ,  H04N19/137 ,  H04N19/186 ,  H04N19/176

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives an average value of motion vector values of two prediction candidates in a prediction candidate list for a merge mode, and registers the average value derived as new motion vector information of a new prediction candidate into the prediction candidate list; and derives new correction processing information regarding correction processing of a prediction image, and registers the new correction processing information derived into the prediction candidate list in association with the new motion vector information.

公开(公告)号：US20240291972A1

公开(公告)日：2024-08-29

申请号：US18657076

申请日：2024-05-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling LIAO ,  Chong Soon Lim ,  Jing Ya Li ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Yusuke Kato ,  Tadamasa Toma ,  Kiyofumi Abe ,  Takahiro Nishi

IPC: H04N19/107 ,  H04N19/176

CPC classification number: H04N19/107 ,  H04N19/176

Abstract: An image encoder includes: circuitry; and a memory coupled to the circuitry. The circuitry, in operation: calculates first values of a current block using intra prediction, the intra prediction being limited to planar mode, the planar mode using multiple reference pixels for each pixel location of the current block; calculates second values of the current block using inter prediction; calculates third values of the current block by weighting the first values and the second values; and encodes the current block using the third values, and in the calculating of the third values, a first weight is applied to the first values and a second weight is applied to the second values, the second weight being different from the first weight.

公开(公告)号：US12075042B2

公开(公告)日：2024-08-27

申请号：US18208380

申请日：2023-06-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Jing Ya Li ,  Han Boon Teo ,  Che-Wei Kuo ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/132 ,  H04N19/169 ,  H04N19/82

CPC classification number: H04N19/117 ,  H04N19/132 ,  H04N19/188 ,  H04N19/82

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: encodes information for deriving a parameter into a header of a bitstream; filters reconstructed samples in a first image using a filtering process, to generate a second image; determines whether the parameter has a predefined value; encodes a third image using the second image when the parameter has the predefined value; and encodes the third image using the first image when the parameter does not have the predefined value.

公开(公告)号：US12069245B2

公开(公告)日：2024-08-20

申请号：US17945629

申请日：2022-09-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling Liao ,  Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Sughosh Pavan Shashidhar ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.

公开(公告)号：US12058329B2

公开(公告)日：2024-08-06

申请号：US18200069

申请日：2023-05-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/13 ,  H04L65/70 ,  H04L65/75 ,  H04N19/176 ,  H04N19/184 ,  H04N19/70

CPC classification number: H04N19/13 ,  H04L65/70 ,  H04L65/75 ,  H04N19/176 ,  H04N19/184 ,  H04N19/70

Abstract: An encoder includes memory and circuitry which: (i) encodes an image block; (ii) when encoding the image block: binarizes coefficient information indicating coefficients of the image block; and controls whether to apply arithmetic encoding to a binary data string obtained by binarizing the coefficient information; and (iii) when binarizing the coefficient information: binarizes the coefficient information according to a first syntax structure when arithmetic encoding is applied to the data string and a predetermined condition is not satisfied; binarizes the coefficient information according to a second syntax structure when arithmetic encoding is applied to the data string and the predetermined condition is satisfied; binarizes the coefficient information according to the second syntax structure when no arithmetic encoding is applied to the data string; and subtracts 1 from a value of an initial non-zero coefficient when no arithmetic encoding is applied to the data string when encoding the image block.

公开(公告)号：US12022118B2

公开(公告)日：2024-06-25

申请号：US17499292

申请日：2021-10-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N19/61 ,  H04N19/103 ,  H04N19/13 ,  H04N19/136 ,  H04N19/176 ,  H04N19/46 ,  H04N19/70 ,  H04N19/91

CPC classification number: H04N19/61 ,  H04N19/13 ,  H04N19/176 ,  H04N19/46 ,  H04N19/70 ,  H04N19/91 ,  H04N19/103 ,  H04N19/136

Abstract: An encoder includes circuitry and memory. In both of a first type of residual coding where an orthogonal transform is applied to a current block and a second type of residual coding where the orthogonal transform is skipped, wherein when a number of CABAC processes is within an allowable range, the circuitry encodes coefficient information flags by CABAC, each of the coefficient information flags relating to a coefficient included in the current block; and otherwise, the circuitry skips the encoding of the coefficient information flags; and the circuitry encodes a remainder value of the coefficient with Golomb-Rice code when the coefficient information flags are encoded; and the circuitry encodes a value of the coefficient with the Golomb-Rice code when the plurality of coefficient information flags are not encoded, wherein the coefficient information flags are partially different between the first type of residual coding and the second type of residual coding.