公开(公告)号：US20110161546A1

公开(公告)日：2011-06-30

申请号：US12978391

申请日：2010-12-23

Applicant: Pai-Ching Huang ,  Tsung-Fu Hung

Inventor： Pai-Ching Huang ,  Tsung-Fu Hung

IPC: G06F13/36

CPC classification number: G06F13/4027 ,  G06F2213/0026

Abstract: A computer system includes a central processing unit (CPU), a north bridge, a south bridge, a bridge and a slot. The north bridge is electrically connected to the CPU. The bridge is electrically connected to the north bridge and the south bridge, and the connector is connected to the bridge. The bridge generates a first data and a second data according to the data packages transmitted from the north bridge and adjusts the output bandwidth of the first data and the second data according to a channel control signal. The south bridge receives or transfers the first data via the bridge so as to communicate with the north bridge. The slot is electrically connected to the bridge and receives or transfers the second data via the bridge so as to communicate with the north bridge.

Abstract translation: 计算机系统包括中央处理单元（CPU），北桥，南桥，桥和槽。 北桥电气连接到CPU。 该桥与北桥和南桥电连接，连接器与桥连接。 桥接器根据从北桥发送的数据包生成第一数据和第二数据，并根据信道控制信号调整第一数据和第二数据的输出带宽。 南桥通过桥接收或传送第一个数据，以便与北桥通信。 插槽电连接到桥接器，并经由桥接器接收或传送第二数据，以便与北桥通信。

公开(公告)号：US08972711B2

公开(公告)日：2015-03-03

申请号：US13039547

申请日：2011-03-03

Applicant: Pei-Hua Sun ,  Pai-Ching Huang ,  Yi-Min Huang ,  Meng-Hsiung Lee ,  Nan-Kun Lo

Inventor： Pei-Hua Sun ,  Pai-Ching Huang ,  Yi-Min Huang ,  Meng-Hsiung Lee ,  Nan-Kun Lo

IPC: G06F9/24 ,  G06F15/177 ,  G06F9/06 ,  G06F15/76

CPC classification number: G06F9/06 ,  G06F15/76

Abstract: A CPU core unlocking device applied to a computer system is provided. The core unlocking device includes a CPU having a plurality of signal terminals and a core unlocking executing unit having a plurality of GPIO ports connected with the corresponding signal terminals of the CPU. The GPIO ports of the core unlocking executing unit generate and transmit and transmit a combination of core unlocking signal to the signal terminals of the CPU to unlock the CPU core.

Abstract translation: 提供了应用于计算机系统的CPU核心解锁装置。 核心解锁装置包括具有多个信号端的CPU和具有与CPU的相应信号端连接的多个GPIO端口的核心解锁执行单元。 核心解锁执行单元的GPIO端口产生并发送核心解锁信号的组合到CPU的信号端，以解锁CPU核心。

公开(公告)号：US08958212B2

公开(公告)日：2015-02-17

申请号：US13337287

申请日：2011-12-27

Applicant: Pai-Ching Huang ,  Tsung-Fu Hung ,  Li-Chien Wu

Inventor： Pai-Ching Huang ,  Tsung-Fu Hung ,  Li-Chien Wu

IPC: H05K7/10 ,  H05K5/02 ,  H01R12/70 ,  H01R12/71

CPC classification number: H05K5/0278 ,  H01R12/7076 ,  H01R12/716 ,  H01R2201/06

Abstract: An electronic device includes a circuit board, a connector and an electronic module. The connector includes an insulating body and a first terminal set. The insulating body includes a concave. The first terminal set is fastened on the insulating body and is electrically connected to the circuit board. The electronic module is detachably disposed in the concave and includes a second terminal set. The second terminal set contacts the first terminal set to be electrically connected to the circuit board.

Abstract translation: 电子设备包括电路板，连接器和电子模块。 连接器包括绝缘体和第一端子组。 绝缘体包括凹面。 第一端子组被固定在绝缘体上并与电路板电连接。 电子模块可拆卸地设置在凹部中并且包括第二端子组。 第二端子组与第一端子组接触以电连接到电路板。

公开(公告)号：US08583849B2

公开(公告)日：2013-11-12

申请号：US13244642

申请日：2011-09-25

Applicant: Pai-Ching Huang ,  Li-Chien Wu

Inventor： Pai-Ching Huang ,  Li-Chien Wu

IPC: G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F1/181 ,  G06F1/184

Abstract: A signal switch connector set is disposed on a motherboard of a computer system. The signal switch connector set is capable of selectively connecting a USB 3.0 signal terminal of a south bridge chip to a USB 3.0 port located at the rear panel of a casing or connecting the USB 3.0 terminal of the south bridge chip to the USB 3.0 port located at the front panel of the casing.

Abstract translation: 信号开关连接器组置于计算机系统的主板上。 信号开关连接器组件能够选择性地将南桥芯片的USB 3.0信号端子连接到位于壳体后面板上的USB 3.0端口或将南桥芯片的USB 3.0端子连接到位于USB 3.0端口 在外壳的前面板上。

公开(公告)号：US08521932B2

公开(公告)日：2013-08-27

申请号：US13050312

申请日：2011-03-17

Applicant: Li-Chien Wu ,  Pai-Ching Huang

Inventor： Li-Chien Wu ,  Pai-Ching Huang

IPC: G06F13/00

CPC classification number: G06F13/364 ,  G06F13/4291

Abstract: A system management bus (SM Bus) system includes an arbitrator; a slave device connected to the arbitrator via an SM Bus; a first master device connected to the arbitrator capable of sending a first start command for communicating with the slave device; and a second master device connected to the arbitrator capable of sending a second start command for communicating with the slave device. The arbitrator set the first master device to have a priority, and when the first start command is being executed and the arbitrator receives the second start command, the arbitrator confirms whether the SM Bus is busy or not after a second predetermined time, and if the SM Bus is not busy, the arbitrator transmits the second start command to the slave devices via the SM Bus.

Abstract translation: 系统管理总线（SM Bus）系统包括一个仲裁器; 通过SM总线连接到仲裁器的从设备; 连接到所述仲裁器的第一主设备，其能够发送用于与所述从设备进行通信的第一启动命令; 以及连接到仲裁器的第二主设备，能够发送用于与从设备进行通信的第二启动命令。 仲裁器将第一主设备设置为具有优先权，并且当第一启动命令正在执行并且仲裁器接收到第二启动命令时，仲裁器在第二预定时间之后确认SM总线是否忙碌，并且如果 SM总线不忙，仲裁器通过SM总线将第二个启动命令发送到从设备。

公开(公告)号：US08380968B2

公开(公告)日：2013-02-19

申请号：US12685228

申请日：2010-01-11

Applicant: Pai-Ching Huang ,  Li-Chien Wu

Inventor： Pai-Ching Huang ,  Li-Chien Wu

IPC: G06F9/00 ,  G06F9/24 ,  G06F15/177

CPC classification number: G06F1/08

Abstract: An overclocking control method cooperates with an overclocking application of a computer system when the overclocking application is started. The overclocking control method includes the steps as follows. A BIOS enters an overclocking mode according to an executing state of the overclocking application. The BIOS receives a first triggering signal outputted from a south bridge chip, and the first triggering signal is generated by the south bridge chip according to a first button of the computer system. The BIOS selects a piece of corresponding overclocking information from a look-up table and loads the overclocking information into a register of the BIOS according to the first triggering signal to control the overclocking of the computer system.

Abstract translation: 当超频应用开始时，超频控制方法与计算机系统的超频应用相配合。 超频控制方法包括以下步骤。 BIOS根据超频应用的执行状态进入超频模式。 BIOS接收从南桥芯片输出的第一触发信号，并且根据计算机系统的第一按钮由南桥芯片产生第一触发信号。 BIOS从查找表中选择一段对应的超频信息，并根据第一触发信号将超频信息加载到BIOS的寄存器中，以控制计算机系统的超频。

公开(公告)号：US20120170238A1

公开(公告)日：2012-07-05

申请号：US13337287

申请日：2011-12-27

Applicant: Pai-Ching Huang ,  Tsung-Fu Hung ,  Li-Chien Wu

Inventor： Pai-Ching Huang ,  Tsung-Fu Hung ,  Li-Chien Wu

IPC: H05K7/10

CPC classification number: H05K5/0278 ,  H01R12/7076 ,  H01R12/716 ,  H01R2201/06

Abstract: An electronic device includes a circuit board, a connector and an electronic module. The connector includes an insulating body and a first terminal set. The insulating body includes a concave. The first terminal set is fastened on the insulating body and is electrically connected to the circuit board. The electronic module is detachably disposed in the concave and includes a second terminal set. The second terminal set contacts the first terminal set to be electrically connected to the circuit board.

Abstract translation: 电子设备包括电路板，连接器和电子模块。 连接器包括绝缘体和第一端子组。 绝缘体包括凹面。 第一端子组被固定在绝缘体上并与电路板电连接。 电子模块可拆卸地设置在凹部中并且包括第二端子组。 第二端子组与第一端子组接触以电连接到电路板。

公开(公告)号：US20120096286A1

公开(公告)日：2012-04-19

申请号：US13241231

申请日：2011-09-23

Applicant: Pai-Ching Huang ,  Che-Wei Lin ,  Hung-Hsiang Chen ,  Chang-Yu Hsieh ,  Li-Chien Wu

Inventor： Pai-Ching Huang ,  Che-Wei Lin ,  Hung-Hsiang Chen ,  Chang-Yu Hsieh ,  Li-Chien Wu

IPC: G06F1/26

CPC classification number: G06F1/263

Abstract: A control circuit of universal serial bus (USB) port includes a charge control unit providing a first operating voltage and a second operating voltage to a first operating voltage end and a second operating voltage end of the USB port, and a first circuit unit coupled to the charge control unit. Furthermore, the first circuit includes a first output end and a second output end. When a external apparatus is inserted into the USB port, the charge control unit connects the first output end and the second output end to a differential positive end and a differential negative end of the USB port, respectively, to enter a rapid charging mode.

Abstract translation: 通用串行总线（USB）端口的控制电路包括向第一工作电压端和USB端口的第二工作电压端提供第一工作电压和第二工作电压的充电控制单元，以及耦合到 充电控制单元。 此外，第一电路包括第一输出端和第二输出端。 当外部设备插入USB端口时，充电控制单元将第一输出端和第二输出端分别连接到USB端口的差分正端和差分负端，以进入快速充电模式。

公开(公告)号：US20100039275A1

公开(公告)日：2010-02-18

申请号：US12481580

申请日：2009-06-10

Applicant: Pai-Ching Huang ,  Chan-Hsuan Kao

Inventor： Pai-Ching Huang ,  Chan-Hsuan Kao

IPC: G08B21/00 ,  G06F17/00 ,  G06F11/07 ,  G06F9/24

CPC classification number: G06F11/326

Abstract: A method for controlling a light signal is provided. The method is suitable for a computer system. The method includes interrupting an original service of the light signal and obtaining the authority to control the light signal. The method also includes controlling the operation of the light signal according to a current status of the computer system.

Abstract translation: 提供了一种用于控制光信号的方法。 该方法适用于计算机系统。 该方法包括中断光信号的原始服务并获得控制光信号的权限。 该方法还包括根据计算机系统的当前状态控制光信号的操作。

公开(公告)号：US20090300378A1

公开(公告)日：2009-12-03

申请号：US12464883

申请日：2009-05-13

Applicant: Jiang-Wen Huang ,  Pai-Ching Huang ,  Ming-Chih Hsu

Inventor： Jiang-Wen Huang ,  Pai-Ching Huang ,  Ming-Chih Hsu

IPC: G06F1/26

CPC classification number: G06F1/3206

Abstract: A power management system is disposed in a computer. The power management system includes a current detecting module and a chipset. The current detecting module is disposed between the power receiving end of an external device and the power cord of the power source of the computer for detecting the current sink by the external device and accordingly outputting a current detecting signal. The chipset adjusts the operating voltage or operating frequency of the external device according to the current detecting signal.

Abstract translation: 电源管理系统设置在计算机中。 电源管理系统包括电流检测模块和芯片组。 电流检测模块设置在外部设备的电力接收端与计算机的电源的电源线之间，用于通过外部设备检测电流接收器，从而输出电流检测信号。 芯片组根据电流检测信号调整外部设备的工作电压或工作频率。