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公开(公告)号：US20060242221A1
公开(公告)日：2006-10-26
申请号：US11114238
申请日：2005-04-26
申请人： Micah McDaniel , Ann Chin , Daniel Kershaw
发明人： Micah McDaniel , Ann Chin , Daniel Kershaw
IPC分类号： G06F7/50
摘要： A data processing apparatus operable to sum data values said data processing apparatus comprising: a plurality of adder logic stages arranged in parallel with each other; control logic operable in response to receipt of a request to sum two data values to forward portions of said two data values to respective ones of said plurality of adder logic stages, such that a first adder logic stage receives a predetermined number of lowest significant bits from each of said two data values and subsequent adder logic stages receive said predetermined number of successively higher significant bits from each of said two data values, each of said plurality of adder logic stages being operable to perform a carry propagate addition of said received portions to generate an intermediate sum, a propagate value and a carry; and further logic stages operable to receive said intermediate sums, carries and propagate values generated from said plurality of adder logic stages and to combine said received intermediate sums, carries and propagate values to produce a sum of said two data values; wherein said control logic is operable in response to receipt of a request to add a third data value to said sum of said two data values, received before said further logic has completed said sum, to forward portions of said third data value to respective ones of said plurality of adder logic stages and to feedback said intermediate sums generated by said plurality of adder logic stages and to selectively feedback a carry generated from a preceding adder logic stage; and said plurality of adder logic stages are operable to perform a carry propagate addition of said fedback intermediate sums and carrys with respective portions of said third data value to generate a plurality of further intermediate sums, further carrys and further propagate values; and wherein said further logic stages are operable to receive said plurality of further intermediate sums, further carries and further propagate values and to combine said received further intermediate sums, carries and propagate values to produce a sum of said three data values.
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公开(公告)号：US07020751B2
公开(公告)日：2006-03-28
申请号：US10201955
申请日：2002-07-25
申请人： Daniel Kershaw
发明人： Daniel Kershaw
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/0804 , G06F13/18
摘要： A data processing system 2 is described including a cache memory 8 and a plurality of DRAM banks 16, 18, 20, 22. A victim select circuit 32 within a cache controller 10 selects victim cache storage lines 28 upon a cache miss such that unlocked cache storage lines are selected in preference to locked cache storage lines, non-dirty cache storage lines are selected in preference to dirty cache storage lines, and cache storage lines requiring a write back to a non-busy DRAM bank are selected in preference to cached storage lines requiring a write back to a busy DRAM storage bank. A DRAM controller 24 is provided that continuously performs a background processing operation whereby dirty cache storage lines 28 within a cache memory 8 are written back to their respective DRAM banks 16, 18, 20, 22 when these are not busy performing other operations and when the cache storage line has a least recently used value below a certain threshold. A bus arbitration circuit 12 is provided that re-arbitrates bus master priorities in dependence upon determined latencies for respective memory access requests. As an example, if a high priority memory access request results a cache miss, with a lower priority memory access request resulting in a cache hit, then the lower priority memory access request will be re-arbitrated to be performed ahead of the normally higher priority memory access request and may be finished before that higher priority memory access request starts to return data words to a data bus 14.
摘要翻译： 描述了数据处理系统2，其包括高速缓存存储器8和多个DRAM存储体18,18,20,22。 高速缓存控制器10内的受害者选择电路32在高速缓存未命中时选择受害者高速缓存存储线28，以便优先选择锁定的高速缓存存储线来解锁高速缓存存储线，优先选择非脏高速缓存存储线， 选择需要写入非忙DRAM库的高速缓存存储线，优先于需要向忙DRAM存储库写回的高速缓存存储线。 提供DRAM控制器24，其连续执行后台处理操作，由此当高速缓存存储器8内的脏高速缓存存储线28在其不忙于执行其他操作时被写回到它们各自的DRAM存储体16,18,20,22，并且当 高速缓存存储线具有低于一定阈值的最近最近使用的值。 提供总线仲裁电路12，其根据对于各个存储器访问请求的确定的延迟重新仲裁总线主机优先级。 作为示例，如果高优先级存储器访问请求导致高速缓存未命中，则优先级较低的存储器访问请求导致高速缓存命中，则优先级较低的存储器访问请求将被重新仲裁以在正常较高优先级之前执行 存储器访问请求，并且可以在更高优先级的存储器访问请求开始将数据字返回到数据总线14之前完成。
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公开(公告)号：US20050210089A1
公开(公告)日：2005-09-22
申请号：US10804181
申请日：2004-03-19
申请人： Daniel Kershaw , Micah McDaniel
发明人： Daniel Kershaw , Micah McDaniel
CPC分类号： G06F7/49921
摘要： A saturating shifter is provided which operates to detect in parallel with a shifting operation whether the result of that shifting operation will require saturating. If saturation is required, then the necessary saturating mask may be determined earlier and accordingly processing speed increased.
摘要翻译： 提供饱和移动器，其操作以与移位操作并行地检测，移位操作的结果是否需要饱和。 如果需要饱和，则可以更早地确定必要的饱和掩模，并且相应地提高处理速度。
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公开(公告)号：US20050125638A1
公开(公告)日：2005-06-09
申请号：US10889365
申请日：2004-07-13
申请人： Simon Ford , Dominic Symes , Daniel Kershaw
发明人： Simon Ford , Dominic Symes , Daniel Kershaw
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30116 , G06F9/30138 , G06F9/3016 , G06F9/30167
摘要： A data processing apparatus and method. The data processing apparatus comprising: a register data store operable to store data elements; an instruction decoder operable to decode a shift instruction; a data processor operable to perform data processing operations controlled by said instruction decoder wherein: in response to said decoded shift instruction, said data processor is operable to specify within said register data store, one or more source registers operable to store a plurality of source data elements of a first size, and one or more destination registers operable to store a corresponding plurality of resultant data elements of a second size, said second size not being equal to said first size; and to perform the following operations in parallel on said plurality of source data elements to produce said corresponding plurality of resultant data elements: shift each of said plurality of source data elements a specified number of places; form at least a part of each of said resultant data elements from information derived from at least a portion of a corresponding one of said plurality of source data elements; store said resultant data elements in said destination register.
摘要翻译： 一种数据处理装置和方法。 该数据处理装置包括：可操作以存储数据元素的寄存器数据存储器; 指令解码器，用于解码移位指令; 数据处理器，用于执行由所述指令解码器控制的数据处理操作，其中：响应于所述解码的移位指令，所述数据处理器可操作以在所述寄存器数据存储器内指定一个或多个源寄存器，其可操作以存储多个源数据 以及一个或多个目的地寄存器，其可操作以存储第二大小的相应多个结果数据元素，所述第二大小不等于所述第一大小; 并且在所述多个源数据元素上并行地执行以下操作以产生所述相应的多个结果数据元素：将所述多个源数据元素中的每一个移位指定数目的位置; 根据从所述多个源数据元素中相应的一个源数据元素的至少一部分导出的信息，形成每个所述结果数据元素的至少一部分; 将所述结果数据元素存储在所述目的地寄存器中。
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公开(公告)号：US08843648B2
公开(公告)日：2014-09-23
申请号：US12472120
申请日：2009-05-26
CPC分类号： G06Q10/10
摘要： Embodiments disclosed herein extend to the use of external access objects in a multi-tenant environment. First and second tenants contract for operations that users of the second tenant will perform in the first tenant. Identity criteria for the users are determined. These users are mapped to an external access object that represents the second tenant users when performing the operations in the first tenant. The external access object is also associated with the resources and/or data that the users of the second tenant will be allowed access to when performing the operations. The users of the second tenant provide a request for access to the resources and/or data to perform operations. Identity criteria are determined and the users are mapped to an external access object based on the identity criteria. It is determined if the user has permission to access the resources and/or data and perform the operations.
摘要翻译： 本文公开的实施例扩展到在多租户环境中使用外部访问对象。 第一和第二租户合同第二租户的用户将在第一租户中履行业务。 确定用户的身份标准。 这些用户被映射到在第一租户执行操作时表示第二租户用户的外部访问对象。 外部访问对象也与在执行操作时允许第二租户的用户访问的资源和/或数据相关联。 第二租户的用户提供访问资源和/或数据以执行操作的请求。 确定身份标准，并且基于身份标准将用户映射到外部访问对象。 确定用户是否具有访问资源和/或数据并执行操作的许可。
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公开(公告)号：US20130103972A1
公开(公告)日：2013-04-25
申请号：US13317593
申请日：2011-10-24
IPC分类号： G06F11/07
CPC分类号： G06F11/1415 , G06F11/0727 , G06F11/076 , G06F11/0787 , G06F2201/86
摘要： A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.
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公开(公告)号：US08200948B2
公开(公告)日：2012-06-12
申请号：US11987720
申请日：2007-12-04
CPC分类号： G06F9/30032 , G06F9/30036
摘要： An apparatus and method are provided for performing re-arrangement operations on data. The data processing apparatus has a register data store with a plurality of registers for storing data, and processing logic for performing a sequence of operations on data including at least one re-arrangement operation. The processing logic has scalar processing logic for performing scalar operations and SIMD processing logic for performing SIMD operations. The SIMD processing logic is responsive to a re-arrangement instruction specifying a family of re-arrangement operations to perform a selected re-arrangement operation from that family on a plurality of data elements constituted by data in one or more registers identified by the re-arrangement instruction. The selected re-arrangement operation is dependent on at least one parameter provided by the scalar processing logic, that parameter identifying a data element width for the data elements on which the selected re-arrangement operation is performed. By such an approach, significant code density improvements can be made in respect of the code executed by the SIMD processing logic.
摘要翻译： 提供了一种用于对数据执行重新排列操作的装置和方法。 数据处理装置具有一个具有多个用于存储数据的寄存器的寄存器数据存储器，以及用于对包括至少一个重新布置操作的数据执行一系列操作的处理逻辑。 处理逻辑具有用于执行标量操作和用于执行SIMD操作的SIMD处理逻辑的标量处理逻辑。 SIMD处理逻辑响应于指定一系列重新布置操作的重新布置指令，以便在由重新配置操作确定的一个或多个寄存器中的数据构成的多个数据元素上从该系列执行所选择的重新排列操作， 安排指导。 所选择的重新布置操作取决于由标量处理逻辑提供的至少一个参数，该参数标识用于执行所选重新布置操作的数据元素的数据元素宽度。 通过这种方法，可以对由SIMD处理逻辑执行的代码进行显着的代码密度改进。
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28.发明申请FLEXIBLE END-POINT COMPLIANCE AND STRONG AUTHENTICATION FOR DISTRIBUTED HYBRID ENTERPRISES 有权分布式混合企业的灵活的端点合规性和强大的认证公开(公告)号：US20110307947A1
公开(公告)日：2011-12-15
申请号：US12815215
申请日：2010-06-14
IPC分类号： G06F7/04
CPC分类号： H04L63/08 , H04L63/102 , H04L2463/082
摘要： Systems, methods and apparatus for accessing at least one resource hosted by at least one server of a cloud service provider. In some embodiments, a client computer sends authentication information associated with a user of the client computer and a statement of health regarding the client computer to an access control gateway deployed in an enterprise's managed network. The access control gateway authenticates the user and determines whether the user is authorized to access the at least one resource hosted in the cloud. If the user authentication and authorization succeeds, the access control gateway requests a security token from a security token service trusted by an access control component in the cloud and forwards the security token to the client computer. The client computer sends the security token to the access component in the cloud to access the at least one resource from the at least one server.
摘要翻译： 用于访问由云服务提供商的至少一个服务器托管的至少一个资源的系统，方法和装置。 在一些实施例中，客户端计算机将与客户端计算机的用户相关联的认证信息和关于客户端计算机的健康声明发送到部署在企业的受管网络中的接入控制网关。 访问控制网关对用户进行认证，并确定用户是否被授权访问云中托管的至少一个资源。 如果用户认证和授权成功，则访问控制网关从云中的访问控制组件信任的安全令牌服务请求安全令牌，并将安全令牌转发给客户端计算机。 客户端计算机将安全令牌发送到云中的访问组件以从至少一个服务器访问该至少一个资源。
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公开(公告)号：US07966466B2
公开(公告)日：2011-06-21
申请号：US12068449
申请日：2008-02-06
IPC分类号： G06F12/00
CPC分类号： G06F12/1483 , G06F9/30076
摘要： Access to memory address space is controlled by memory access control circuitry using access control data. The ability to change the access control data is controlled by domain control circuitry. Whether or not an instruction stored within a particular domain, being a set of memory addresses, is able to modify the access control data is dependent upon the domain concerned. Thus, the ability to change access control data can be restricted to instructions stored within particular defined locations within the memory address space thereby enhancing security. This capability allows systems to be provided in which call forwarding to an operating system can be enforced via call forwarding code and where trusted regions of the memory address space can be established into which a secure operating system may write data with increased confidence that that data will only be accessible by trusted software executing under control of a non-secure operating system.
摘要翻译： 使用访问控制数据的存储器访问控制电路控制对存储器地址空间的访问。 更改访问控制数据的能力由域控制电路控制。 作为一组存储器地址的存储在特定域内的指令是否能够修改访问控制数据取决于所涉及的域。 因此，改变访问控制数据的能力可以被限制为存储在存储器地址空间内的特定定义位置内的指令，从而增强安全性。 该功能允许提供系统，其中可以通过呼叫转移代码来实施对操作系统的呼叫转移，并且可以建立存储器地址空间的可信区域，安全操作系统可以以更高的置信度写入数据，该数据将 只能通过在非安全操作系统的控制下执行的可信软件来访问。
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30.发明授权公开(公告)号：US07949835B2
公开(公告)日：2011-05-24
申请号：US11230498
申请日：2005-09-21
IPC分类号： G06F12/00
CPC分类号： G06F12/145 , G06F12/1081 , G06F12/1491
摘要： A data processing apparatus and method are provided for controlling access to memory. The data processing apparatus comprises main processing logic operable to execute a sequence of instructions in order to perform a process, and subsidiary processing logic operable to perform at least part of the process on behalf of the main processing logic. A memory is provided that is accessible by the main processing logic when performing the process, the main processing logic defining a portion of the memory to be allocated memory accessible to the subsidiary processing logic when performing part of the process on behalf of the main processing logic. Further, a memory management unit is provided that is programmable by the main processing logic and operable to control access to the allocated memory by the subsidiary processing logic. The main processing logic is arranged to program the memory management unit such that for an access request issued by the subsidiary processing logic relating to the allocated memory, the memory management unit produces a memory address and one or more associated memory attributes identifying one or more properties of the allocated memory at that memory address.
摘要翻译： 提供了一种用于控制对存储器的访问的数据处理装置和方法。 数据处理装置包括主处理逻辑，其可操作以执行指令序列以便执行处理，以及辅助处理逻辑可操作以代表主处理逻辑执行至少一部分处理。 提供在执行处理时可由主处理逻辑访问的存储器，主处理逻辑定义了当代表主处理逻辑执行部分处理时辅助处理逻辑可访问的待分配存储器的一部分的存储器 。 此外，提供存储器管理单元，其可由主处理逻辑编程并且可操作以通过辅助处理逻辑控制对所分配的存储器的访问。 主处理逻辑被布置为对存储器管理单元进行编程，使得对于与分配的存储器相关的辅助处理逻辑发出的访问请求，存储器管理单元产生存储器地址和一个或多个相关联的存储器属性，其标识一个或多个属性 在该存储器地址处分配的存储器。
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