公开(公告)号：US20100122044A1

公开(公告)日：2010-05-13

申请号：US12308405

申请日：2006-07-11

申请人： Simon Ford ,  Dominic Hugo Symes ,  Alastair Reid

发明人： Simon Ford ,  Dominic Hugo Symes ,  Alastair Reid

IPC分类号： G06F9/38 ,  G06F15/80 ,  G06F12/00

CPC分类号： G06F9/30036 ,  G06F9/345 ,  G06F9/3838

摘要： A parallel processing technique is described for performing parallel processing operations upon N-dimensional arrays of data elements for which a corresponding N-dimensional Scoreboard of status data is held. Hazard checking for data dependencies upon data elements within the N-dimensional array of data elements is performed by looking up the corresponding status value within the Scoreboard. The status data for a given data element within the Scoreboard is located at a position which can be derived from the position of the data elements within its N-dimensional array. Thus, a two-dimensional array of video macroblocks can have a corresponding two-dimensional Scoreboard of status data indicating whether individual macroblocks have, for example, either already been deblocked or have not already been deblocked.

摘要翻译： 描述了一种并行处理技术，用于对保持状态数据的相应N维记分板的数据元素的N维阵列执行并行处理操作。 通过查看记分板内的相应状态值来执行数据元素N维数组内的数据元素的数据依赖性的危害检查。 记分板内的给定数据元素的状态数据位于可从其N维阵列内的数据元素的位置导出的位置。 因此，视频宏块的二维阵列可以具有状态数据的相应的二维记分板，该状态数据指示单个宏块是否已经被解锁或尚未被解块。

公开(公告)号：US20080114937A1

公开(公告)日：2008-05-15

申请号：US11976315

申请日：2007-10-23

申请人： Alastair Reid ,  Edmund Grimley-Evans ,  Simon Ford

发明人： Alastair Reid ,  Edmund Grimley-Evans ,  Simon Ford

IPC分类号： G06F13/28

CPC分类号： G06F11/362 ,  G06F11/3636

摘要： A computer implemented tool is provided for assisting in the mapping of a computer program to an asymmetric multiprocessing apparatus 2 incorporating an asymmetric memory hierarchy formed of a plurality of memories 12, 14. An at least partial architectural description 22, 40 is provided as an input variable to the tool and used to infer missing annotations within a source computer program 24, such as which functions are to be executed by which execution mechanisms 4, 6, 8 and which variables are to be stored within which memories 12, 14. The tool also adds mapping support commands, such as cache flush commands, cache invalidate commands, DMA move commands and the like as necessary to support the mapping of the computer program to the asymmetric multiprocessing apparatus 2.

摘要翻译： 提供了一种计算机实现的工具，用于帮助将计算机程序映射到并入由多个存储器12,14形成的非对称存储器层级的非对称多处理装置2。 提供至少部分架构描述22,40作为工具的输入变量，并且用于推断源计算机程序24内的丢失注释，诸如哪些功能将由哪个执行机构4,6,8以及哪些 变量被存储在哪个存储器12,14中。 该工具还根据需要添加诸如缓存刷新命令，缓存无效命令，DMA移动命令等映射支持命令，以支持计算机程序到非对称多处理装置2的映射。

公开(公告)号：US20050154773A1

公开(公告)日：2005-07-14

申请号：US10930846

申请日：2004-09-01

申请人： Simon Ford ,  David Seal ,  Wilco Dijkstra

发明人： Simon Ford ,  David Seal ,  Wilco Dijkstra

IPC分类号： G06F7/50 ,  G06F7/52 ,  G06F9/30 ,  G06F9/302 ,  G06F9/305 ,  G06F9/315 ,  G06F9/318 ,  G06F15/00

CPC分类号： G06F9/30167 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3016 ,  G06F9/3017

摘要： The present invention provides a data processing apparatus and method for performing data processing operations on floating point data elements. The data processing apparatus has processing logic for performing data processing operations on the floating point data elements, and decode logic operable to decode a data processing instruction in order to determine a corresponding data processing operation to be performed by the processing logic. The data processing instruction has an m-bit immediate value encoded therein. Further, constant generation logic is provided to perform a logical operation on the m-bit immediate value in order to generate an n-bit floating point constant for use as at least one input floating point data element for the processing logic when performing the corresponding data processing operation. The values “n” and “m” are integers, and n is greater than m. This approach provides a particularly efficient technique for generating floating point constants.

摘要翻译： 本发明提供一种用于对浮点数据元素执行数据处理操作的数据处理装置和方法。 数据处理装置具有用于对浮点数据元素执行数据处理操作的处理逻辑，以及可操作以对数据处理指令进行解码的解码逻辑，以便确定由处理逻辑执行的相应数据处理操作。 数据处理指令具有在其中编码的m位立即值。 此外，提供恒定生成逻辑以对m位立即值执行逻辑运算，以便在执行相应数据时产生用于处理逻辑的至少一个输入浮点数据元素的n位浮点常数 处理操作。 值“n”和“m”是整数，n大于m。 该方法提供了一种特别有效的生成浮点常数的技术。

公开(公告)号：US20050125638A1

公开(公告)日：2005-06-09

申请号：US10889365

申请日：2004-07-13

申请人： Simon Ford ,  Dominic Symes ,  Daniel Kershaw

发明人： Simon Ford ,  Dominic Symes ,  Daniel Kershaw

IPC分类号： G06F9/38 ,  G06F9/00 ,  G06F9/30 ,  G06F9/312 ,  G06F15/80 ,  G06T1/20

CPC分类号： G06F9/30025 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/30167

摘要： A data processing apparatus and method. The data processing apparatus comprising: a register data store operable to store data elements; an instruction decoder operable to decode a shift instruction; a data processor operable to perform data processing operations controlled by said instruction decoder wherein: in response to said decoded shift instruction, said data processor is operable to specify within said register data store, one or more source registers operable to store a plurality of source data elements of a first size, and one or more destination registers operable to store a corresponding plurality of resultant data elements of a second size, said second size not being equal to said first size; and to perform the following operations in parallel on said plurality of source data elements to produce said corresponding plurality of resultant data elements: shift each of said plurality of source data elements a specified number of places; form at least a part of each of said resultant data elements from information derived from at least a portion of a corresponding one of said plurality of source data elements; store said resultant data elements in said destination register.

摘要翻译： 一种数据处理装置和方法。 该数据处理装置包括：可操作以存储数据元素的寄存器数据存储器; 指令解码器，用于解码移位指令; 数据处理器，用于执行由所述指令解码器控制的数据处理操作，其中：响应于所述解码的移位指令，所述数据处理器可操作以在所述寄存器数据存储器内指定一个或多个源寄存器，其可操作以存储多个源数据 以及一个或多个目的地寄存器，其可操作以存储第二大小的相应多个结果数据元素，所述第二大小不等于所述第一大小; 并且在所述多个源数据元素上并行地执行以下操作以产生所述相应的多个结果数据元素：将所述多个源数据元素中的每一个移位指定数目的位置; 根据从所述多个源数据元素中相应的一个源数据元素的至少一部分导出的信息，形成每个所述结果数据元素的至少一部分; 将所述结果数据元素存储在所述目的地寄存器中。

公开(公告)号：US20090210678A1

公开(公告)日：2009-08-20

申请号：US11922557

申请日：2005-08-01

申请人： Simon Ford

发明人： Simon Ford

IPC分类号： G06F9/302

CPC分类号： G06F7/49936

摘要： A data processing apparatus operate to process floating point operands is disclosed. The data processing apparatus comprises: an instruction decoder operable to decode an instruction for processing floating point operands; and a data processor operable to perform data processing operations controlled by the instruction decoder wherein: in response to the decoded instruction indicating operation according to a flush-to-zero semantic, the data processor is operable to process the floating point operands in accordance with the decoded instruction such that floating point operands having a denormal value are treated as zero operands; and in response to the decoded instruction indicating operation according to a denormal semantic, the data processor is operable to process the floating point operands in accordance with the decoded instruction such that floating point operands having a denormal value are treated as denormal operands.

摘要翻译： 公开了处理浮点操作数的操作数据处理装置。 数据处理装置包括：指令解码器，用于解码用于处理浮点操作数的指令; 以及数据处理器，其可操作以执行由所述指令解码器控制的数据处理操作，其中响应于所述解码指令指示根据刷新至零语义的操作，所述数据处理器可操作以根据所述指令译码器处理所述浮点操作数 解码指令，使得具有非正常值的浮点操作数被视为零操作数; 并且响应于指示根据非正常语义的操作的解码指令，数据处理器可操作以根据解码的指令来处理浮点操作数，使得具有异常值的浮点操作数被视为反正态操作数。

公开(公告)号：US20070171731A1

公开(公告)日：2007-07-26

申请号：US11300599

申请日：2005-12-15

申请人： Simon Ford ,  David Howard

发明人： Simon Ford ,  David Howard

IPC分类号： G11C7/10

CPC分类号： H03K19/0016 ,  H03K2217/0036

摘要： Leakage current from a circuit for handling data is reduced using leakage control circuit operable in a leakage reduction mode. The data handling circuit comprises data handling logic operable to receive an input data value and to output and output data value. The data handling circuit also comprises a latch operable to latch the output data value in response to a clock signal having a clock period. Both the leakage control circuitry and the latch are controlled dependent upon the same clock signal and the leakage control circuitry is controlled such that it is in a leakage reduction mode for a time less than the clock period. This approach enables leakage reduction to be provided in circuits which are still operational and is particularly suited to data handling circuits that employ frequency scaling.

摘要翻译： 用于处理数据的电路的泄漏电流使用可在泄漏降低模式下工作的泄漏控制电路来减少。 数据处理电路包括可操作以接收输入数据值并输出和输出数据值的数据处理逻辑。 数据处理电路还包括可操作以响应于具有时钟周期的时钟信号来锁存输出数据值的锁存器。 泄漏控制电路和锁存器都依赖于相同的时钟信号进行控制，并且泄漏控制电路被控制使得它在低于时钟周期的时间内处于泄漏减小模式。 这种方法使得能够在仍然可操作的电路中提供泄漏减少，并且特别适合于采用频率缩放的数据处理电路。

公开(公告)号：US06958718B2

公开(公告)日：2005-10-25

申请号：US10889217

申请日：2004-07-13

申请人： Dominic Hugo Symes ,  Simon Ford ,  Andrew Christopher Rose

发明人： Dominic Hugo Symes ,  Simon Ford ,  Andrew Christopher Rose

IPC分类号： G06F9/38 ,  G06F7/00 ,  G06F9/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/312 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355 ,  H03M7/00

CPC分类号： G06F9/3004 ,  G06F9/30181 ,  G06F9/342 ,  G06F9/383

摘要： A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result register D3. Out-of-range index values result in the corresponding locations within the result register being left unchanged U. In this way, an offset can be applied to index values held and then those index values reused with the table registers D0, D1 being reloaded with a different portion of a table so as to give the effect of a larger table than can be directly supported by the number of table registers available.

公开(公告)号：US20050198473A1

公开(公告)日：2005-09-08

申请号：US10889366

申请日：2004-07-13

申请人： Simon Ford

发明人： Simon Ford

IPC分类号： G06F9/38 ,  G06F7/76 ,  G06F9/305 ,  G06F9/34 ,  G06F15/80 ,  G06F9/00

CPC分类号： G06F7/762 ,  G06F7/76 ,  G06F7/768 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3822

摘要： A data processing apparatus, method and computer program product. The apparatus comprising: a register data store comprising at least three general purpose registers each operable to store a plurality of data elements; an instruction decoder operable to decode a multiplex instruction; a data processor operable to process said plurality of data elements in parallel, said data processor being controlled by said instruction decoder; and in response to said decoded multiplex instruction, said data processor being operable to specify: two of said at least three general-purpose registers as source registers, each operable to store a plurality of source data elements; a further one of said at least three registers as a control register operable to store a plurality of control values; and one of said control, or said two source registers as a destination register operable to store a plurality of resultant data elements; wherein in response to each of said plurality of control values said data processor is operable to select a corresponding data element from one of said two source registers, and to store said corresponding data element as a resultant data element in said destination register.

摘要翻译： 数据处理装置，方法和计算机程序产品。 该装置包括：寄存器数据存储器，包括至少三个通用寄存器，每个通用寄存器可操作以存储多个数据元素; 指令解码器，用于解码多路复用指令; 数据处理器，可操作以并行处理所述多个数据元素，所述数据处理器由所述指令解码器控制; 并且响应于所述解码的多路复用指令，所述数据处理器可操作以指定：所述至少三个通用寄存器中的两个作为源寄存器，每个可用于存储多个源数据元素; 所述至少三个寄存器中的另一个作为可操作以存储多个控制值的控制寄存器; 以及所述控制或所述两个源寄存器之一作为可操作以存储多个结果数据元素的目的地寄存器; 其中响应于所述多个控制值中的每一个，所述数据处理器可操作以从所述两个源寄存器之一中选择相应的数据元素，并将所述对应的数据元素作为结果数据元素存储在所述目的寄存器中。

公开(公告)号：US20050125640A1

公开(公告)日：2005-06-09

申请号：US10889318

申请日：2004-07-13

申请人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

发明人： Simon Ford ,  Dominic Symes ,  Andrew Rose ,  David Lutz ,  Christopher Hinds

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/345 ,  G06F9/38 ,  G06F15/80

CPC分类号： G06F9/3887 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3822 ,  G06F9/3885

摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements occupying different lanes of parallel processing in at least one of the registers. Access logic is provided which is responsive to a single access instruction to move a plurality of data elements between a chosen one of the lanes in specified registers and a structure within memory having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is operation to arrange the plurality of data elements as they are moved such that data elements of different components are stored in different specified registers within the chosen lane whilst in memory the data elements are stored as the structure.

摘要翻译： 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以并行地执行对至少一个寄存器中的并行处理的不同通道的多个数据元素的数据处理操作。 提供了访问逻辑，其响应于单个访问指令，以在指定寄存器中的所选择的一个通道中移动多个数据元素，以及在具有结构格式的存储器内的结构，所述结构格式具有多个组件。 单个访问指令标识结构格式中的组件的数量，并且访问逻辑是在移动多个数据元素时排列多个数据元素的操作，使得不同组件的数据元素存储在所选择的通道内的不同指定的寄存器中，同时 存储数据元素作为结构存储。

公开(公告)号：US20050125635A1

公开(公告)日：2005-06-09

申请号：US10889315

申请日：2004-07-13

申请人： Dominic Symes ,  Simon Ford

发明人： Dominic Symes ,  Simon Ford

IPC分类号： G06F9/38 ,  G06F9/06 ,  G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F12/02 ,  G06F15/00 ,  G06F15/80

CPC分类号： G06F9/3013 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

摘要： A data processing system 2 is provided including a scalar register store 4 and a SIMD register store 20. Dedicated register transfer instructions are provided which serve to move a data value between a selected data element position/lane within a SIMD register of the SIMD register data store 20 and a scalar register within the scalar register store 4. This type of register transfer instruction allows particular data elements to be picked out of and inserted into a SIMD register in a manner which advantageously improves overall efficiency. A further type of register transfer instruction is provided which copies a data value taken from a scalar register into all positions of a specified SIMD register.

摘要翻译： 提供了包括标量寄存器存储器4和SIMD寄存器存储器20的数据处理系统2。 提供了专用寄存器传送指令，其用于在SIMD寄存器数据存储器20的SIMD寄存器内的选定数据元素位置/通道与标量寄存器存储器4内的标量寄存器之间移动数据值。 这种类型的寄存器传送指令允许特定的数据元素以有利地提高整体效率的方式被选出并插入到SIMD寄存器中。 提供了另一种类型的寄存器传送指令，其将从标量寄存器获取的数据值复制到指定SIMD寄存器的所有位置。