公开(公告)号：US08490535B1

公开(公告)日：2013-07-23

申请号：US13213190

申请日：2011-08-19

申请人： Charles Moore ,  Thomas Mooty

发明人： Charles Moore ,  Thomas Mooty

IPC分类号： F41A21/00

CPC分类号： F41A21/30 ,  F41A21/325 ,  F41A21/34

摘要： A flash hider, a sound suppressor and a quick-disconnect coupler that holds the sound suppressor to a flash hider is disclosed. The quick-disconnect coupler enables the suppressor to be attached to the flash hider so that the hider forms a nozzle at the entrance to the sound suppressor to facilitate the operation of the suppressor. The coupler includes a collar that threads to the first part of the suppressor over plural holes formed therein. Camming latches set in these holes are held firmly against flat surfaces on the exterior of the flash hider by the collar. A spring lock holds the collar against rotation until it is released.

摘要翻译： 公开了一种闪光灯，一个抑制器和一个将隔音器保持在闪光灯上的快速断开耦合器。 快速断开连接器使得抑制器能够附接到闪光灯，使得吊具在声音抑制器的入口处形成喷嘴以便于抑制器的操作。 联接器包括一个轴环，该轴环在其中形成的多个孔上螺纹连接到抑制器的第一部分。 设置在这些孔中的凸轮锁扣通过轴环牢固地保持在闪光灯外部的平坦表面上。 弹簧锁将套环保持旋转直到释放。

公开(公告)号：US08490534B1

公开(公告)日：2013-07-23

申请号：US13211405

申请日：2011-08-17

申请人： Charles Moore

发明人： Charles Moore

IPC分类号： F41A21/00

CPC分类号： F41A21/34

摘要： A flash hider has a central bore for receiving the barrel of a firearm at one end and three tapered tines at the opposing end with a gap formed between each pair of adjacent tines. Just past the muzzle-seat in the central bore is a flared entrance leading to the gaps thereby allowing hot air and combustion gases to expand radially through the gaps between the tines, thereby cooling the hot air and gases. The lateral faces of the tines are stepped to cause turbulent mixing of the cooler air surrounding the flash hider with the exiting gases so as to further expand and cool in order to prevent re-ignition and thereby reduce secondary flash. Long tines help to hide all but direct viewing of primary flash.

摘要翻译： 闪光灯具有用于在一端接收枪支的中心孔，并且在相对端具有三个锥形尖齿，在每对相邻齿之间形成间隙。 恰好通过中心孔中的枪口座是一个扩口入口，导致间隙，从而允许热空气和燃烧气体径向扩张通过尖齿之间的间隙，从而冷却热空气和气体。 尖齿的侧面是阶梯式的，以使闪光灯周围的较冷空气与出射气体湍流混合，以进一步膨胀和冷却，以防止再点火，从而减少二次闪光。 长齿有助于隐藏所有但直接观看主闪光灯。

公开(公告)号：US08253810B2

公开(公告)日：2012-08-28

申请号：US11987869

申请日：2007-12-05

申请人： Charles Myers ,  Michael J. Brosnan ,  Charles Moore ,  Richard A. Baumgartner ,  Christopher Silsby ,  Brian J. Misek

发明人： Charles Myers ,  Michael J. Brosnan ,  Charles Moore ,  Richard A. Baumgartner ,  Christopher Silsby ,  Brian J. Misek

IPC分类号： H04N5/228 ,  H04N3/14 ,  H04N5/335 ,  G03B17/00

CPC分类号： H04N5/23248 ,  H04N5/23254 ,  H04N5/2327

摘要： An imaging pixel array and associated method and system are disclosed in which the array contains first pixels each having a first photo-conversion device, and second pixels each having a first photo-conversion device and a second photo-conversion device. The first photo-conversion devices are configured to acquire an image during a first integration period. The second photo-conversion devices are configured to acquire a plurality of images during the first integration period. A circuit uses the plurality of image signals and determines from them relative motion between the array and an image during a portion of the first integration period and provides a signal representing the motion which is used for image stabilization.

摘要翻译： 公开了一种成像像素阵列及其相关联的方法和系统，其中阵列包含每个具有第一光转换装置的第一像素，以及每个具有第一光转换装置和第二光转换装置的第二像素。 第一光转换装置被配置为在第一积分周期期间获取图像。 第二光转换装置被配置为在第一积分周期期间获取多个图像。 电路使用多个图像信号，并且在第一积分周期的一部分期间从其确定阵列与图像之间的相对运动，并且提供表示用于图像稳定的运动的信号。

公开(公告)号：US08167084B1

公开(公告)日：2012-05-01

申请号：US13032804

申请日：2011-02-23

申请人： Charles Moore

发明人： Charles Moore

IPC分类号： F41A21/30

CPC分类号： F41A21/30

摘要： A sound suppressor suppresses sound and flash by creating interacting paths of gas. While a first portion of the gas follows a first path through the suppressor, a second portion of the gas is diverted radially from the first path to a second path and then repeatedly made to cross the first path by a series of baffles with alternating radial passages so that the two portions of gas interfere and interact with each other, and therefore quickly give up much of their kinetic energy before they exit the suppressor. Preferably, the baffles defining the second path impart a swirl to the second portion of gas to cause the present suppressor to flush itself of carbon and metal particles. The interaction of the two portions also accelerates completion of combustion of the gas to thereby reduce flash.

摘要翻译： 声音抑制器通过创建气体相互作用的路径来抑制声音和闪光。 当气体的第一部分遵循通过抑制器的第一路径时，气体的第二部分从第一路径径向转向第二路径，然后通过具有交替的径向通道的一系列挡板重复地穿过第一路径 使得气体的两部分彼此干涉并相互作用，因此在它们离开抑制器之前迅速放弃其大部分动能。 优选地，限定第二路径的挡板给气体的第二部分赋予涡流，以使本发明的抑制器自身冲洗碳和金属颗粒。 两部分的相互作用也加速了气体的燃烧完成，从而减少了闪光。

公开(公告)号：US20080071991A1

公开(公告)日：2008-03-20

申请号：US11981482

申请日：2007-10-31

申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

摘要翻译： 微处理器以100 MHz内部时钟频率执行100个本机MIPS峰值性能。 中央处理单元（CPU）指令集是硬连线的，允许大多数指令在一个周期内执行。 “流通”设计允许下一条指令在先前指令完成之前启动，从而提高性能。 微处理单元（MPU）包含52个通用寄存器，包括16个全局数据寄存器，一个索引寄存器，一个计数寄存器，一个16深可寻址寄存器/返回堆栈以及一个18深操作数堆栈。 两个堆栈都包含顶部元素中的索引寄存器，缓存在芯片上，并在需要时自动溢出并从外部存储器中重新填充。 堆栈最小化数据移动，并在过程调用，参数传递和变量赋值期间最小化存储器访问。 此外，MPU还包含一个模式/状态寄存器和41个用于I / O，控制，配置和状态的本地寻址寄存器。 CPU包含高性能零操作数双堆栈架构MPU和执行指令传输数据，计数事件，测量时间和执行其他与时序相关的功能的输入输出处理器（IOP）。 零操作数堆栈架构消除了操作数位。 堆栈还可以在过程内和跨过程中最小化寄存器保存和加载，从而允许较短的指令序列和更快的运行代码。 指令简单易于解码和执行，允许MPU和IOP在单个时钟周期内发出和完成指令，每个时钟周期为100个本机MIPS峰值执行。 每次执行指令提取或预取时，CPU使用8位操作码，最多可从内存中获取四条指令。 这些指令可以重复，而不会从内存重新读取。 当直接连接到DRAM而没有高速缓存时，这将保持高性能。

公开(公告)号：US20070250682A1

公开(公告)日：2007-10-25

申请号：US11731747

申请日：2007-03-30

申请人： Charles Moore ,  John Rible ,  Jeffrey Fox

发明人： Charles Moore ,  John Rible ,  Jeffrey Fox

IPC分类号： G06F15/00

CPC分类号： G06F15/8023 ,  G06F9/5066 ,  G06F9/547

摘要： A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 24 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output. Mechanisms are described for communications between computers (12) and the outside environment.

摘要翻译： 计算机阵列（10）具有用于完成更大任务的多个计算机（12），其被划分成较小的任务，每个较小的任务分配给一个或多个计算机（12）。 每个计算机（12）可以被配置为用于特定功能，并且与外部计算机（12）相关联的各个输入/输出电路（26）特别适用于特定的输入/输出功能。 布置在计算机阵列（10）中的24台计算机（12）的示例具有集中式计算核心（34），其中靠近管芯（14）边缘的计算机（12）被配置为用于输入和/或输出。 描述了用于计算机（12）和外部环境之间的通信的机制。

公开(公告)号：US20060188039A1

公开(公告)日：2006-08-24

申请号：US11062149

申请日：2005-02-18

申请人： Mark Wahl ,  Aaron Volz ,  Charles Moore

发明人： Mark Wahl ,  Aaron Volz ,  Charles Moore

IPC分类号： H04L27/06

CPC分类号： G06F17/11

摘要： A method and apparatus is presented for performing an n-dimensional gradient search. A state machine is implemented to manage the initial location of the search, increment a counter used to count a search, generate locations (i.e., settings) of the search and the errors associated with the search. The state machine manages an n-dimensional counter. In one embodiment, a tertiary counter is implemented. The tertiary counter performs a three-state count and then rolls over to the beginning count at the end of the three states. The three-state count corresponds to a location of a search, a location of the search minus one, and a location of the search plus one.

摘要翻译： 呈现用于执行n维梯度搜索的方法和装置。 实施状态机以管理搜索的初始位置，增加用于对搜索进行计数的计数器，生成搜索的位置（即设置）和与搜索相关联的错误。 状态机管理一个n维计数器。 在一个实施例中，实现了第三计数器。 三级计数器执行三态计数，然后在三个状态结束时翻转到开始计数。 三态计数对应于搜索的位置，搜索的位置减去一个，以及搜索的位置加一。

公开(公告)号：US20060097719A1

公开(公告)日：2006-05-11

申请号：US10984515

申请日：2004-11-09

申请人： Charles Moore

发明人： Charles Moore

IPC分类号： G01N27/82

CPC分类号： G01N27/82

摘要： An inspection carriage provides for remote inspection of the Z-shroud and snubber regions of the blades of a steam turbine, while the blades remain in the turbine. The carriage includes a non-destructive inspection probe such as a meandering wave magnetometer probe or eddy current probe mounted on a slider, so that the probe may be moved along a radial axis, skew axis, axial axis, and rotation axis. Cameras are provided on the carriage so that the probe may be remotely guided into the region to be inspected.

公开(公告)号：US20050262553A1

公开(公告)日：2005-11-24

申请号：US11081792

申请日：2005-03-15

申请人： William Bialick ,  Russell Housley ,  Charles Moore ,  Duane Linsenbardt

发明人： William Bialick ,  Russell Housley ,  Charles Moore ,  Duane Linsenbardt

IPC分类号： G06F1/00 ,  G06F21/00 ,  H04L9/00 ,  H04L9/32

CPC分类号： G06F21/10 ,  G06F21/335 ,  G06F2211/007 ,  G06F2221/2115 ,  H04L9/3234 ,  H04L9/3263 ,  H04L2209/56

摘要： A licensing attribute certificate enables a trusted computing base to enforce access to a computing resource by a computer application. The licensing attribute certificate can contain enforcement data which limits the use of the computing resource. The licensing attribute certificate can also contain information allowing for the tracking of licensing data about the use of the computing resource. The use of a licensing attribute certificate to enforce access to a computing resource can allow products to be fielded which have their capability limited to a specific subset of functions. The enforcement data, the licensing data, and the data limiting the application to a specific subset of functions are cryptographically bound to the computing resource using a licensing attribute certificate according to the invention. Prior to allowing access to the computing resource by the computer application, a trusted computing base strongly authenticates that usage via the licensing attribute certificate.

公开(公告)号：US20050228904A1

公开(公告)日：2005-10-13

申请号：US10801942

申请日：2004-03-16

申请人： Charles Moore

发明人： Charles Moore

IPC分类号： G06F3/00

CPC分类号： G06F9/5066 ,  G06F9/5044

摘要： A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 25 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output.

摘要翻译： 计算机阵列（10）具有用于完成更大任务的多个计算机（12），其被划分成较小的任务，每个较小的任务分配给一个或多个计算机（12）。 每个计算机（12）可以被配置为用于特定功能，并且与外部计算机（12）相关联的各个输入/输出电路（26）特别适用于特定的输入/输出功能。 布置在计算机阵列（10）中的25台计算机（12）的示例具有集中计算核心（34），其中靠近管芯（14）边缘的计算机（12）被配置为用于输入和/或输出。