公开(公告)号：US20120005375A1

公开(公告)日：2012-01-05

申请号：US12703220

申请日：2010-03-16

申请人： Russell Fish

发明人： Russell Fish

IPC分类号： G06F15/16

CPC分类号： H04L41/0893 ,  H04L67/10

摘要： A technique for organizing a plurality of computers such that message broadcast, content searching, and computer identification of the entire collection or a subset of the entire collection may be performed quickly without the use of a controlling computer. The technique describes the creation, operation, and maintenance of a connection scheme by which each computer in the collection appears to be the top level of a hierarchical array. The maintenance of this hierarchical connection scheme allows one to many communications throughout the collection of computers to scale geometrically rather than linearly.

公开(公告)号：US20080091920A1

公开(公告)日：2008-04-17

申请号：US11981237

申请日：2007-10-31

申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

IPC分类号： G06F9/00 ,  G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

公开(公告)号：US20080077911A1

公开(公告)日：2008-03-27

申请号：US11981278

申请日：2007-10-31

申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

IPC分类号： G06F9/44

CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

公开(公告)号：US20070271442A1

公开(公告)日：2007-11-22

申请号：US11881284

申请日：2007-07-26

申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

IPC分类号： G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

公开(公告)号：US20060230163A1

公开(公告)日：2006-10-12

申请号：US11386173

申请日：2006-03-22

申请人： Russell Fish

发明人： Russell Fish

IPC分类号： G06F15/16

CPC分类号： H04L63/0218 ,  H04L29/12509 ,  H04L61/2567 ,  H04L63/029

摘要： The disclosed system describes a means for internetworked computers protected behind blocking firewalls to communicate directly with other internetworked computers protected behind blocking firewalls. A trusted computer helps establish a connection between the two protected computers, but all subsequent communications takes place directly between the two protected computers.

摘要翻译： 所公开的系统描述了一种用于互联网络计算机的装置，其在防火墙之后被保护以直接与阻塞防火墙后保护的其他互联网络计算机通信。 可信计算机有助于建立两台受保护计算机之间的连接，但所有后续通信都直接在两台受保护的计算机之间进行。

公开(公告)号：US08984256B2

公开(公告)日：2015-03-17

申请号：US12147332

申请日：2008-06-26

申请人： Russell Fish

发明人： Russell Fish

IPC分类号： G06F9/38 ,  G06F15/78 ,  G06F9/30 ,  G06F9/32 ,  G06F9/34 ,  G06F12/08 ,  G06F15/80

CPC分类号： G06F15/80 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/325 ,  G06F9/34 ,  G06F9/38 ,  G06F9/3851 ,  G06F9/3885 ,  G06F12/0848 ,  G06F12/0875 ,  G06F13/28 ,  G06F15/7846 ,  G06F15/8007 ,  Y02D10/13

摘要： In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors; wherein each of the processors is operable to process a de minimis instruction set, and wherein each of the processors comprises local caches dedicated to each of at least three specific registers in the processor. In another aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors, wherein each of the processors is operable to process an instruction set optimized for thread-level parallel processing and wherein each processor accesses the internal data bus of the computer memory on the chip and the internal data bus is the width of one row of the memory.

摘要翻译： 一方面，本发明包括一种系统，包括：（a）单个芯片上的多个并行处理器; 和（b）位于芯片上并由每个处理器访问的计算机存储器; 其中每个处理器可操作以处理最小指令集，并且其中每个处理器包括专用于处理器中的至少三个特定寄存器中的每一个的本地高速缓存。 在另一方面，本发明包括一种系统，包括：（a）在单个芯片上的多个并行处理器; 和（b）位于芯片上并由每个处理器访问的计算机存储器，其中每个处理器可操作以处理针对线程级并行处理优化的指令集，并且其中每个处理器访问计算机存储器的内部数据总线 在芯片上和内部数据总线是一行内存的宽度。

公开(公告)号：US20080072021A1

公开(公告)日：2008-03-20

申请号：US11981453

申请日：2007-10-31

申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

IPC分类号： G06F9/302

CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

公开(公告)号：US4549825A

公开(公告)日：1985-10-29

申请号：US633609

申请日：1984-07-23

申请人： Russell Fish, III ,  James R. Yurchenco

发明人： Russell Fish, III ,  James R. Yurchenco

IPC分类号： H04L21/00 ,  B41J29/02

CPC分类号： H04L21/00

摘要： An electronic mail terminal 10 that includes a keyboard 12, multi-character display 14, thermal printer 22, tape drive 118, and communication and control circuitry. The tape drive and printer mount to molded-in features of a base housing 20. A printed circuit board 28 containing the communication and control circuitry and the display is mounted to molded-in features of the base housing. The keyboard plugs into the printed circuit board from above and is supported at the sides by stand-offs in the base housing. A cover housing 88 mates with molded-in features of the base housing. The tape drive mechanism includes cassette guides 98 and 376 that are molded into the base and cover housings and a spring loaded motor mount that automatically compensates for wear and positioning tolerances. A printer carriage motor 184 drives a toothed belt 182 to position a carriage 138 which holds a thermal print head 140. An optical encoder 146 and a mechanical switch 194 provide position feedback of carriage position to the control circuitry. A paper advance motor 256 advances the paper through a worm gear train 256, 262 with position feedback provided by a mechanical switch 280. The printer carriage is a molded plastic runner to which the toothed belt and the thermal print head attaches. A metal clip 340 provides an easily removable mounting for the print head.

摘要翻译： 包括键盘12，多字符显示器14，热敏打印机22，磁带驱动器118以及通信和控制电路的电子邮件终端10。 带式驱动器和打印机安装件用于模制成基座壳体20的特征。包含通信和控制电路和显示器的印刷电路板28被安装到基座壳体的模制特征中。 键盘从上方插入印刷电路板，并通过底座中的支架在侧面支撑。 盖壳体88与基座壳体的模制特征配合。 带驱动机构包括模制到基座和盖壳体中的盒引导件98和376以及自动补偿磨损和定位公差的弹簧加载电机安装座。 打印机滑架马达184驱动齿形带182以定位保持热打印头140的滑架138.光学编码器146和机械开关194提供滑架位置到控制电路的位置反馈。 纸张提前电动机256通过具有由机械开关280提供的位置反馈的蜗轮系256,262推进纸张。打印机滑架是齿形带和热打印头附接到的模制塑料流道。 金属夹340提供用于打印头的容易移除的安装。

公开(公告)号：US4524242A

公开(公告)日：1985-06-18

申请号：US465040

申请日：1983-02-08

申请人： Russell Fish, III ,  James R. Yurchenco

发明人： Russell Fish, III ,  James R. Yurchenco

IPC分类号： H04L21/00

CPC分类号： H04L21/00

摘要： An electronic mail terminal 10 that includes a keyboard 12, multi-character display 14, thermal printer 22, tape drive 118, and communication and control circuitry. The tape drive and printer mount to molded-in features of a base housing 20. A printed circuit board 28 containing the communication and control circuitry and the display is mounted to molded-in features of the base housing. The keyboard plugs into the printed circuit board from above and is supported at the sides by stand-offs in the base housing. A cover housing 88 mates with molded-in features of the base housing. The tape drive mechanism includes cassette guides 98 and 376 that are molded into the base and cover housings and a spring loaded motor mount that automatically compensates for wear and positioning tolerances. A printer carriage motor 184 drives a toothed belt 182 to position a carriage 138 which holds a thermal print head 140. An optical encoder 146 and a mechanical switch 194 provide position feedback of carriage position to the control circuitry. A paper advance motor 256 advances the paper through a worm gear train 256, 262 with position feedback provided by a mechanical switch 280. The printer carriage is a molded plastic runner to which the toothed belt and the thermal print head attaches. A metal clip 340 provides an easily removable mounting for the print head.

摘要翻译： 包括键盘12，多字符显示器14，热敏打印机22，磁带驱动器118以及通信和控制电路的电子邮件终端10。 带式驱动器和打印机安装件用于模制成基座壳体20的特征。包含通信和控制电路和显示器的印刷电路板28被安装到基座壳体的模制特征中。 键盘从上方插入印刷电路板，并通过底座中的支架在侧面支撑。 盖壳体88与基座壳体的模制特征配合。 带驱动机构包括模制到基座和盖壳体中的盒引导件98和376以及自动补偿磨损和定位公差的弹簧加载电机安装座。 打印机滑架马达184驱动齿形带182以定位保持热打印头140的滑架138.光学编码器146和机械开关194提供滑架位置到控制电路的位置反馈。 纸张提前电动机256通过具有由机械开关280提供的位置反馈的蜗轮系256,262推进纸张。打印机滑架是齿形带和热打印头附接到的模制塑料流道。 金属夹340提供用于打印头的容易移除的安装。

公开(公告)号：US20120014250A1

公开(公告)日：2012-01-19

申请号：US12703218

申请日：2010-03-16

申请人： Russell Fish

发明人： Russell Fish

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L12/26

CPC分类号： H04L41/0893 ,  H04L67/10

摘要： A technique for organizing a plurality of computers such that message broadcast, content searching, and computer identification of the entire collection or a subset of the entire collection may be performed quickly without the use of a controlling computer. The technique describes the creation, operation, and maintenance of a connection scheme by which each computer in the collection appears to be the top level of a hierarchical array. The maintenance of this hierarchical connection scheme allows one to many communications throughout the collection of computers to scale geometrically rather than linearly.

摘要翻译： 一种用于组织多个计算机的技术，使得可以快速执行整个集合的整个集合的消息广播，内容搜索和计算机标识，而不需要使用控制计算机。 该技术描述了连接方案的创建，操作和维护，通过该方案，收集中的每台计算机似乎是分层数组的顶层。 这种分层连接方案的维护允许在整个计算机集合中进行多次通信以在几何上进行比例而不是线性化。