公开(公告)号：US08185662B2

公开(公告)日：2012-05-22

申请号：US12719214

申请日：2010-03-08

申请人： Kenneth Michael Valk

发明人： Kenneth Michael Valk

IPC分类号： G06F15/16

CPC分类号： G06F15/16

摘要： A method and circuit for implementing enhanced transport layer flow control, and a design structure on which the subject circuit resides are provided. The transport layer provides multiple virtual lanes to application layers, and provides buffering and credit control for the multiple virtual lanes. A source transport layer sends a credit request message to a destination transport layer for an outstanding packets transmission. The packets are sent only responsive to the credit request being granted by the destination transport layer. Respective switch and link layer are constructed to support only a single virtual lane, regardless of how many virtual lanes are supported at the application and transport layers. As a result, the routing, buffering, and flow control at the respective switch and link layer are simplified.

摘要翻译： 一种用于实现增强的传输层流控制的方法和电路，以及设置有该主题电路所在的设计结构。 传输层为应用层提供多个虚拟通道，并为多个虚拟通道提供缓冲和信用控制。 源传输层向目的地传输层发送信用请求消息，用于未完成的分组传输。 仅响应于目的地传输层授予的信用请求而发送分组。 不管开关和链路层是如何支持单个虚拟通道，不管应用层和传输层支持多少个虚拟通道。 结果，简化了各个交换机和链路层的路由，缓冲和流控制。

公开(公告)号：US20110219139A1

公开(公告)日：2011-09-08

申请号：US12719214

申请日：2010-03-08

申请人： Kenneth Michael Valk

发明人： Kenneth Michael Valk

IPC分类号： G06F15/16

CPC分类号： G06F15/16

摘要： A method and circuit for implementing enhanced transport layer flow control, and a design structure on which the subject circuit resides are provided. The transport layer provides multiple virtual lanes to application layers, and provides buffering and credit control for the multiple virtual lanes. A source transport layer sends a credit request message to a destination transport layer for an outstanding packets transmission. The packets are sent only responsive to the credit request being granted by the destination transport layer. Respective switch and link layer are constructed to support only a single virtual lane, regardless of how many virtual lanes are supported at the application and transport layers. As a result, the routing, buffering, and flow control at the respective switch and link layer are simplified.

摘要翻译： 一种用于实现增强的传输层流控制的方法和电路，以及设置有该主题电路所在的设计结构。 传输层为应用层提供多个虚拟通道，并为多个虚拟通道提供缓冲和信用控制。 源传输层向目的地传输层发送信用请求消息，用于未完成的分组传输。 仅响应于目的地传输层授予的信用请求而发送分组。 不管开关和链路层是如何支持单个虚拟通道，不管应用层和传输层支持多少个虚拟通道。 结果，简化了各个交换机和链路层的路由，缓冲和流控制。

公开(公告)号：US20110208954A1

公开(公告)日：2011-08-25

申请号：US12709662

申请日：2010-02-22

申请人： Wayne Melvin Barrett ,  Kenneth Michael Valk

发明人： Wayne Melvin Barrett ,  Kenneth Michael Valk

IPC分类号： G06F12/14 ,  G06F9/24 ,  G06F1/12

CPC分类号： H04L63/0457 ,  G06F1/12 ,  G06F13/00 ,  H04L2209/12

摘要： A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.

摘要翻译： 一种用于实现多个串行链路之间的已知加扰关系的方法和电路，以及设置有该主题电路所在的设计结构。 发送线性反馈移位寄存器（LFSR）与多个串行链路中的每一个一起提供，用于加扰发送的数据。 每个多个串行链路提供接收线性反馈移位寄存器（LFSR），用于解扰接收到的数据。 每个发送LFSR被初始化为唯一值。 每个发送的LFSR向接收LFSR传送当前唯一的值以使发送LFSR同步并且接收LFSR以开始加扰和解扰数据。

公开(公告)号：US20110206141A1

公开(公告)日：2011-08-25

申请号：US12709733

申请日：2010-02-22

申请人： Wayne Melvin Barrett ,  Kenneth Michael Valk

发明人： Wayne Melvin Barrett ,  Kenneth Michael Valk

IPC分类号： H04L27/00

CPC分类号： H04L5/1438

摘要： A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.

摘要翻译： 一种用于实现串行链路训练序列的方法和电路，以及设置该对象电路所在的设计结构。 发射机设备发送训练序列（TS）模式; 则发射机设备在预定义的持续时间内发送随机数据。 重复发送TS模式，然后发送固定持续时间的随机数据的步骤。 检测分离了随机数据的预定时间间隔的多个TS模式的接收机设备执行接收机初始化步骤。 接收机装置执行多个接收机初始化步骤，包括例如获取字节锁定和链路宽度确定。

公开(公告)号：US07996621B2

公开(公告)日：2011-08-09

申请号：US11776731

申请日：2007-07-12

申请人： Jeffrey Douglas Brown ,  Russell Dean Hoover ,  Eric Oliver Mejdrich ,  Kenneth Michael Valk

发明人： Jeffrey Douglas Brown ,  Russell Dean Hoover ,  Eric Oliver Mejdrich ,  Kenneth Michael Valk

IPC分类号： G06F12/12

CPC分类号： G06F12/0895 ,  Y02D10/13

摘要： According to embodiments of the invention, a step value and a step-interval cache coherency protocol may be used to update and invalidate data stored within cache memory. A step value may be an integer value and may be stored within a cache directory entry associated with data in the memory cache. Upon reception of a cache read request, along with the normal address comparison to determine if the data is located within the cache a current step value may be compared with the stored step value to determine if the data is current. If the step values match, the data may be current and a cache hit may occur. However, if the step values do not match, the requested data may be provided from another source. Furthermore, an application may update the current step value to invalidate old data stored within the cache and associated with a different step value.

摘要翻译： 根据本发明的实施例，可以使用步长值和步进间隔高速缓存一致性协议来更新和使存储在高速缓冲存储器中的数据无效。 步数值可以是整数值，并且可以存储在与存储器高速缓存中的数据相关联的高速缓存目录条目中。 在接收到缓存读取请求时，连同正常地址比较以确定数据是否位于高速缓存内，可以将当前步长值与存储的步长值进行比较，以确定数据是否为当前值。 如果步数值匹配，数据可能是当前的，并且可能会发生高速缓存命中。 然而，如果步骤值不匹配，则可以从另一个源提供所请求的数据。 此外，应用程序可以更新当前步骤值以使存储在高速缓存中并与不同步长值相关联的旧数据无效。