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1.发明授权Implementing serial link training patterns separated by random data for training a serial link in an interconnect system 有权实现由随机数据分离的串行链路训练模式，用于训练互连系统中的串行链路公开(公告)号：US08275922B2
公开(公告)日：2012-09-25
申请号：US12709733
申请日：2010-02-22
IPC分类号： G06F13/42
CPC分类号： H04L5/1438
摘要： A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.
摘要翻译： 一种用于实现串行链路训练序列的方法和电路，以及设置该对象电路所在的设计结构。 发射机设备发送训练序列（TS）模式; 则发射机设备在预定义的持续时间内发送随机数据。 重复发送TS模式，然后发送固定持续时间的随机数据的步骤。 检测分离了随机数据的预定时间间隔的多个TS模式的接收机设备执行接收机初始化步骤。 接收机装置执行多个接收机初始化步骤，包括例如获取字节锁定和链路宽度确定。
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2.发明授权Early return indication for read exclusive requests in shared memory architecture 有权在共享内存架构中读取独占请求的早期返回指示公开(公告)号：US07536514B2
公开(公告)日：2009-05-19
申请号：US11225655
申请日：2005-09-13
IPC分类号： G06F12/06
CPC分类号： G06F13/1663 , G06F12/0817
摘要： An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data if the source has an exclusive copy of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources. The early return indication may also serves as an early coherency indication in that the first communications interface is no longer required to wait for updating of a coherency directory to complete prior to forwarding the return data over the communication link.
摘要翻译： 早期返回指示用于在从与第二通信接口耦合的多个源中的任一个接收到响应之前通知第一通信接口，使得第一通信接口在接收时可以由第一通信接口使用返回数据 来自返回数据的源，如果源具有返回数据的排他副本。 通过这样做，第一通信接口通常可以准备通过其相关联的通信链路转发返回数据，使得一旦数据从源中检索出来，数据可以很少或没有等待时间转发，并且可能能够启动返回 在从其他来源接收到所有响应之前通过通信链路的数据。 早期返回指示还可以用作早期一致性指示，因为在通过通信链路转发返回数据之前，第一通信接口不再需要等待更新相干性目录来完成。
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3.发明授权公开(公告)号：US08010682B2
公开(公告)日：2011-08-30
申请号：US11023706
申请日：2004-12-28
CPC分类号： G06F12/0817 , G06F2212/507
摘要： In a shared memory architecture, early coherency indication is used to notify a communications interface, prior to the data for a memory request is returned, and prior to updating a coherency directory in response to the memory request, that the return data can be used by the communications interface when it is received thereby from a source of the return data. By doing so, the communications interface can often begin forwarding the return data over its associated communication link with little or no latency once the data is retrieved from its source. In addition, the communications interface is often no longer required to wait for updating of the coherency directory to complete prior to forwarding the return data over the communication link. As such, the overall latency for handling the memory request is typically reduced.
摘要翻译： 在共享存储器架构中，早期一致性指示用于在返回存储器请求的数据之前以及在响应于存储器请求更新一致性目录之前通知通信接口，返回数据可以由 当从返回数据的来源接收通信接口时。 通过这样做，一旦数据从其源中检索，通信接口通常可以在几乎没有或没有延迟的情况下开始转发其相关联的通信链路上的返回数据。 此外，通常不需要通信接口在通过通信链路转发返回数据之前等待更新相干性目录来完成。 因此，处理存储器请求的总体延迟通常减少。
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4.发明授权公开(公告)号：US08804960B2
公开(公告)日：2014-08-12
申请号：US12709662
申请日：2010-02-22
CPC分类号： H04L63/0457 , G06F1/12 , G06F13/00 , H04L2209/12
摘要： A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.
摘要翻译： 一种用于实现多个串行链路之间的已知加扰关系的方法和电路，以及设置有该主题电路所在的设计结构。 发送线性反馈移位寄存器（LFSR）与多个串行链路中的每一个一起提供，用于加扰发送的数据。 每个多个串行链路提供接收线性反馈移位寄存器（LFSR），用于解扰接收到的数据。 每个发送LFSR被初始化为唯一值。 每个发送的LFSR向接收LFSR传送当前唯一的值以使发送LFSR同步并且接收LFSR以开始加扰和解扰数据。
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公开(公告)号：US20110208954A1
公开(公告)日：2011-08-25
申请号：US12709662
申请日：2010-02-22
CPC分类号： H04L63/0457 , G06F1/12 , G06F13/00 , H04L2209/12
摘要： A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.
摘要翻译： 一种用于实现多个串行链路之间的已知加扰关系的方法和电路，以及设置有该主题电路所在的设计结构。 发送线性反馈移位寄存器（LFSR）与多个串行链路中的每一个一起提供，用于加扰发送的数据。 每个多个串行链路提供接收线性反馈移位寄存器（LFSR），用于解扰接收到的数据。 每个发送LFSR被初始化为唯一值。 每个发送的LFSR向接收LFSR传送当前唯一的值以使发送LFSR同步并且接收LFSR以开始加扰和解扰数据。
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公开(公告)号：US20110206141A1
公开(公告)日：2011-08-25
申请号：US12709733
申请日：2010-02-22
IPC分类号： H04L27/00
CPC分类号： H04L5/1438
摘要： A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.
摘要翻译： 一种用于实现串行链路训练序列的方法和电路，以及设置该对象电路所在的设计结构。 发射机设备发送训练序列（TS）模式; 则发射机设备在预定义的持续时间内发送随机数据。 重复发送TS模式，然后发送固定持续时间的随机数据的步骤。 检测分离了随机数据的预定时间间隔的多个TS模式的接收机设备执行接收机初始化步骤。 接收机装置执行多个接收机初始化步骤，包括例如获取字节锁定和链路宽度确定。
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7.发明申请公开(公告)号：US20110243154A1
公开(公告)日：2011-10-06
申请号：US12749812
申请日：2010-03-30
CPC分类号： H04L1/0079 , H03M13/09 , H04L1/0072
摘要： A method and circuit for implementing variable length packets to embed extra control information in an interconnect system, and a design structure on which the subject circuit resides are provided. Packets are defined to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in the packet header. The packet header also includes its own CRC field. When a nonzero ETE flit count field is received in an incoming packet from an incoming link, the specified number of embedded ETE flits is removed from the packet and is used the same as if the control information arrived in its own packet.
摘要翻译： 一种用于实现可变长度分组以在互连系统中嵌入额外控制信息的方法和电路，以及提供了主题电路所在的设计结构。 分组被定义为在分组报头中的分组（Flit）计数字段内包括端到端（ETE）流单元。 分组报头还包括其自己的CRC字段。 当在来自传入链路的传入分组中接收到非零的ETE飞行计数字段时，从分组中删除指定数量的嵌入式ETE飞行，并且与控制信息到达自己的分组一样被使用。
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8.发明授权Atomic ownership change operation for input/output (I/O) bridge device in clustered computer system 失效集群计算机系统中输入/输出（I / O）桥接器件的原子所有权更改操作公开(公告)号：US06754753B2
公开(公告)日：2004-06-22
申请号：US09844584
申请日：2001-04-27
申请人： Bruce Leroy Beukema , Richard Charles Booth , David Robert Engebretsen , Thomas Rembert Sand , Kenneth Michael Valk
发明人： Bruce Leroy Beukema , Richard Charles Booth , David Robert Engebretsen , Thomas Rembert Sand , Kenneth Michael Valk
IPC分类号： G06F1516
CPC分类号： G06F9/52
摘要： A clustered computer system, bridge device and method include support for an atomic ownership change operation that ensures orderly and reliable ownership management of an input/output (I/O) bridge device. A lock indicator is associated with a bridge device, and is used to indicate a “locked” or “unlocked” status of the bridge device. Whenever the lock indicator indicates that the bridge device is unlocked, an atomic operation such as a read request to a lock indicator register is utilized to both set the indicator to indicate a locked status for the bridge device, and to associate the bridge device with a source node that initiated the atomic operation. In connection with the lock indicator, write access to one or more configuration parameter registers is controlled such that only the node that is associated with the bridge device is permitted to update such configuration parameter registers.
摘要翻译： 集群计算机系统，桥接器件和方法包括支持原子所有权更改操作，确保输入/输出（I / O）桥接器件的有序可靠的所有权管理。 锁定指示器与桥接设备相关联，并用于指示桥接设备的“锁定”或“解锁”状态。 每当锁定指示器指示桥接设备被解锁时，利用诸如对锁定指示器寄存器的读取请求的原子操作来将指示器设置为指示桥接设备的锁定状态，并且将桥接设备与 源节点启动原子操作。 与锁定指示器相关联，控制对一个或多个配置参数寄存器的写入访问，使得仅允许与桥接设备相关联的节点更新这样的配置参数寄存器。
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9.发明授权Storing and using the history of data transmission errors to assure data integrity 有权存储和使用数据传输错误的历史以确保数据完整性公开(公告)号：US06643818B1
公开(公告)日：2003-11-04
申请号：US09443521
申请日：1999-11-19
申请人： Kenneth Michael Valk
发明人： Kenneth Michael Valk
IPC分类号： H04L100
CPC分类号： H04L1/0063
摘要： A method and apparatus is disclosed which enhances the integrity of transmitted data or detects when random data is being received which might indicate that a receiver or a transmitter is open or that random data is otherwise being transmitted. A stream of data transmitted in packets having an error code associated with each packet is received into a receiver. The receiver has an error code checker to check the error code of each packet to determine if the data packet has been transmitted error-free. The results of the error checks for n sequential packets are stored in a shift register or counter. An incoming packet then undergoes an error code check and the results of the previous n sequential packets are considered. If a predetermined number of the previous n sequential packets has a transmission error n, then the method decides to reject or accept the error packet based on the quality of data integrity. When a 32-bit CRC error code is used, an 8-bit shift register is sufficient to prevent the acceptance of a packet of random data that may otherwise be accepted.
摘要翻译： 公开了一种增强传输数据的完整性或检测何时正在接收可能指示接收机或发射机打开或者随机数据被另外传输的随机数据的方法和装置。 在具有与每个分组相关联的错误代码的分组中传输的数据流被接收到接收机中。 接收机有一个错误代码检查器，用于检查每个数据包的错误代码，以确定数据包是否已经无误传输。 n个顺序包的错误检查结果存储在移位寄存器或计数器中。 然后，传入的数据包经历错误代码检查，并考虑先前的n个顺序数据包的结果。 如果预定数量的先前n个顺序分组具有传输错误n，则该方法基于数据完整性的质量决定拒绝或接受错误分组。 当使用32位CRC错误代码时，8位移位寄存器足以防止接受可能被接受的随机数据包。
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10.发明授权Implementing ordered and reliable transfer of packets while spraying packets over multiple links 失效在多个链路上分发数据包时，实现有序可靠的数据包传输公开(公告)号：US08358658B2
公开(公告)日：2013-01-22
申请号：US12727545
申请日：2010-03-19
IPC分类号： H04L12/28
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.
摘要翻译： 一种用于在通过多个链路喷射分组时实现分组的有序和可靠传送的方法和电路，并且提供了主题电路所在的设计结构。 每个源互连芯片保持喷射掩模，其包括用于每个目的地芯片的多个可用链路，用于在本地机架互连系统的多个链路上喷射分组。 每个数据包被分配在源互连芯片中的端到端（ETE）序列号，其表示来自源设备的有序分组流中的分组位置。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收到的喷射数据包重新排序为正确的顺序。
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