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1.发明授权Implementing serial link training patterns separated by random data for training a serial link in an interconnect system 有权实现由随机数据分离的串行链路训练模式，用于训练互连系统中的串行链路公开(公告)号：US08275922B2
公开(公告)日：2012-09-25
申请号：US12709733
申请日：2010-02-22
IPC分类号： G06F13/42
CPC分类号： H04L5/1438
摘要： A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.
摘要翻译： 一种用于实现串行链路训练序列的方法和电路，以及设置该对象电路所在的设计结构。 发射机设备发送训练序列（TS）模式; 则发射机设备在预定义的持续时间内发送随机数据。 重复发送TS模式，然后发送固定持续时间的随机数据的步骤。 检测分离了随机数据的预定时间间隔的多个TS模式的接收机设备执行接收机初始化步骤。 接收机装置执行多个接收机初始化步骤，包括例如获取字节锁定和链路宽度确定。
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2.发明授权公开(公告)号：US08010682B2
公开(公告)日：2011-08-30
申请号：US11023706
申请日：2004-12-28
CPC分类号： G06F12/0817 , G06F2212/507
摘要： In a shared memory architecture, early coherency indication is used to notify a communications interface, prior to the data for a memory request is returned, and prior to updating a coherency directory in response to the memory request, that the return data can be used by the communications interface when it is received thereby from a source of the return data. By doing so, the communications interface can often begin forwarding the return data over its associated communication link with little or no latency once the data is retrieved from its source. In addition, the communications interface is often no longer required to wait for updating of the coherency directory to complete prior to forwarding the return data over the communication link. As such, the overall latency for handling the memory request is typically reduced.
摘要翻译： 在共享存储器架构中，早期一致性指示用于在返回存储器请求的数据之前以及在响应于存储器请求更新一致性目录之前通知通信接口，返回数据可以由 当从返回数据的来源接收通信接口时。 通过这样做，一旦数据从其源中检索，通信接口通常可以在几乎没有或没有延迟的情况下开始转发其相关联的通信链路上的返回数据。 此外，通常不需要通信接口在通过通信链路转发返回数据之前等待更新相干性目录来完成。 因此，处理存储器请求的总体延迟通常减少。
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3.发明授权Early return indication for read exclusive requests in shared memory architecture 有权在共享内存架构中读取独占请求的早期返回指示公开(公告)号：US07536514B2
公开(公告)日：2009-05-19
申请号：US11225655
申请日：2005-09-13
IPC分类号： G06F12/06
CPC分类号： G06F13/1663 , G06F12/0817
摘要： An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data if the source has an exclusive copy of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources. The early return indication may also serves as an early coherency indication in that the first communications interface is no longer required to wait for updating of a coherency directory to complete prior to forwarding the return data over the communication link.
摘要翻译： 早期返回指示用于在从与第二通信接口耦合的多个源中的任一个接收到响应之前通知第一通信接口，使得第一通信接口在接收时可以由第一通信接口使用返回数据 来自返回数据的源，如果源具有返回数据的排他副本。 通过这样做，第一通信接口通常可以准备通过其相关联的通信链路转发返回数据，使得一旦数据从源中检索出来，数据可以很少或没有等待时间转发，并且可能能够启动返回 在从其他来源接收到所有响应之前通过通信链路的数据。 早期返回指示还可以用作早期一致性指示，因为在通过通信链路转发返回数据之前，第一通信接口不再需要等待更新相干性目录来完成。
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4.发明授权公开(公告)号：US08804960B2
公开(公告)日：2014-08-12
申请号：US12709662
申请日：2010-02-22
CPC分类号： H04L63/0457 , G06F1/12 , G06F13/00 , H04L2209/12
摘要： A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.
摘要翻译： 一种用于实现多个串行链路之间的已知加扰关系的方法和电路，以及设置有该主题电路所在的设计结构。 发送线性反馈移位寄存器（LFSR）与多个串行链路中的每一个一起提供，用于加扰发送的数据。 每个多个串行链路提供接收线性反馈移位寄存器（LFSR），用于解扰接收到的数据。 每个发送LFSR被初始化为唯一值。 每个发送的LFSR向接收LFSR传送当前唯一的值以使发送LFSR同步并且接收LFSR以开始加扰和解扰数据。
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公开(公告)号：US20110208954A1
公开(公告)日：2011-08-25
申请号：US12709662
申请日：2010-02-22
CPC分类号： H04L63/0457 , G06F1/12 , G06F13/00 , H04L2209/12
摘要： A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.
摘要翻译： 一种用于实现多个串行链路之间的已知加扰关系的方法和电路，以及设置有该主题电路所在的设计结构。 发送线性反馈移位寄存器（LFSR）与多个串行链路中的每一个一起提供，用于加扰发送的数据。 每个多个串行链路提供接收线性反馈移位寄存器（LFSR），用于解扰接收到的数据。 每个发送LFSR被初始化为唯一值。 每个发送的LFSR向接收LFSR传送当前唯一的值以使发送LFSR同步并且接收LFSR以开始加扰和解扰数据。
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公开(公告)号：US20110206141A1
公开(公告)日：2011-08-25
申请号：US12709733
申请日：2010-02-22
IPC分类号： H04L27/00
CPC分类号： H04L5/1438
摘要： A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.
摘要翻译： 一种用于实现串行链路训练序列的方法和电路，以及设置该对象电路所在的设计结构。 发射机设备发送训练序列（TS）模式; 则发射机设备在预定义的持续时间内发送随机数据。 重复发送TS模式，然后发送固定持续时间的随机数据的步骤。 检测分离了随机数据的预定时间间隔的多个TS模式的接收机设备执行接收机初始化步骤。 接收机装置执行多个接收机初始化步骤，包括例如获取字节锁定和链路宽度确定。
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公开(公告)号：US07426672B2
公开(公告)日：2008-09-16
申请号：US11116624
申请日：2005-04-28
申请人： Wayne Melvin Barrett , Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Wayne Melvin Barrett , Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
摘要翻译： 提供了一种用于在计算机系统中实现处理器总线推测数据完成的方法和装置。 计算机系统中的存储器控制器将未校正的数据从存储器发送到处理器总线。 存储器控制器还将未校正的数据应用于纠错码（ECC）校验和校正电路。 当检测到单个位错误（SBE）时，校正的数据在未校正的数据之后被发送到处理器总线预定数量的周期。
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公开(公告)号：US20080222489A1
公开(公告)日：2008-09-11
申请号：US12127118
申请日：2008-05-27
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
摘要翻译： 提供了一种用于在计算机系统中实现处理器总线推测数据完成的方法和装置。 计算机系统中的存储器控制器将未校正的数据从存储器发送到处理器总线。 存储器控制器还将未校正的数据应用于纠错码（ECC）校验和校正电路。 当检测到单个位错误（SBE）时，校正的数据在未校正的数据之后被发送到处理器总线预定数量的周期。
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公开(公告)号：US07392353B2
公开(公告)日：2008-06-24
申请号：US11004199
申请日：2004-12-03
CPC分类号： G06F13/1626
摘要： Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.
摘要翻译： 无条件优先级被提供给由多个存储器请求者共享的数据总线上的按顺序数据传输的无序数据传输。 通过总是优先处理诸如写入和/或缓存到高速缓存数据传输之类的按顺序传输的延迟读取数据传输的无序传输，确保没有较新的命令或事务对延迟产生负面影响 的旧命令或事务。
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公开(公告)号：US07890708B2
公开(公告)日：2011-02-15
申请号：US12029630
申请日：2008-02-12
IPC分类号： G06F12/00
CPC分类号： G06F13/1626
摘要： Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.
摘要翻译： 无条件优先级被提供给由多个存储器请求者共享的数据总线上的按顺序数据传输的无序数据传输。 通过总是优先处理诸如写入和/或缓存到高速缓存数据传输之类的按顺序传输的延迟读取数据传输的无序传输，确保没有较新的命令或事务对延迟产生负面影响 的旧命令或事务。
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