公开(公告)号：US20160239442A1

公开(公告)日：2016-08-18

申请号：US14622017

申请日：2015-02-13

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  RICHARD ALAN STEWART ,  SUBRATO KUMAR DE

IPC: G06F13/26 ,  G06F13/18

CPC classification number: G06F13/26 ,  G06F13/1636 ,  G06F13/1663 ,  G06F13/18

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing a signal to each of a plurality of processors on a system on chip (SoC) for scheduling the maintenance event; each of the plurality of processors independently generating in response to the signal a corresponding schedule notification for the maintenance event; and the memory controller determining when to execute the maintenance event in response to receiving one or more of the schedule notifications generated by the plurality of processors and based on a processor priority scheme.

Abstract translation: 公开了用于调度易失性存储器维护事件的系统，方法和计算机程序。 一个实施例是一种方法，包括：存储器控制器，其确定用于经由存储器数据接口耦合到存储器控制器的易失性存储器设备执行维护事件的服务时间（ToS）窗口; 所述存储器控制器为片上系统（SoC）上的多个处理器中的每一个提供信号，用于调度所述维护事件; 所述多个处理器中的每一个独立地响应于所述信号产生用于所述维护事件的对应的调度通知; 并且所述存储器控制器响应于接收到由所述多个处理器产生的所述调度通知中的一个或多个并且基于处理器优先级方案来确定何时执行所述维护事件。

公开(公告)号：US20160239441A1

公开(公告)日：2016-08-18

申请号：US14621929

申请日：2015-02-13

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI

IPC: G06F13/26 ,  G06F13/18

CPC classification number: G06F13/26 ,  G06F9/4818 ,  G06F13/18

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing an interrupt signal to a processing unit; determining a priority for the maintenance event; and scheduling the maintenance event according to the priority.

Abstract translation: 公开了用于调度易失性存储器维护事件的系统，方法和计算机程序。 一个实施例是一种方法，包括：存储器控制器，其确定用于经由存储器数据接口耦合到存储器控制器的易失性存储器设备执行维护事件的服务时间（ToS）窗口; 所述存储器控制器向处理单元提供中断信号; 确定维护事件的优先级; 并根据优先级调度维护事件。

公开(公告)号：US20150243373A1

公开(公告)日：2015-08-27

申请号：US14187279

申请日：2014-02-23

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  XIANGYU DONG ,  JUNGWON SUH ,  JUNG PILL KIM ,  DEEPTI VIJAYALAKSHMI SRIRAMAGIRI

IPC: G11C29/44 ,  G06F11/20 ,  G06F11/10

CPC classification number: G11C29/44 ,  G06F11/1048 ,  G06F11/1076 ,  G06F11/2053 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C2029/4402

Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

Abstract translation: 公开了用于内核屏蔽动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。 一种这样的方法包括：检测和校正与动态随机存取存储器（DRAM）中的物理地址相关联的单位错误; 从DRAM接收与物理地址相关联的错误数据; 将接收到的错误数据存储在位于非易失性存储器中的故障地址表中; 并且如果与物理地址相关联的错误数量超过错误计数阈值，则退出对应于物理地址的内核页面。

公开(公告)号：US20150242213A1

公开(公告)日：2015-08-27

申请号：US14187272

申请日：2014-02-23

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  DEXTER TAMIO CHUN ,  DHAMIM PACKER ALI ,  GREGORY AMERIADA UVIEGHARA ,  ZHONGZE WANG

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F8/66 ,  G06F12/0638

Abstract: Various embodiments of methods and systems for flexible read only memory (“ROM”) storage of coded instructions in a portable computing device (“PCD”) are disclosed. Because certain instructions and/or data associated with a primary boot loader (“PBL”) may be defective or in need of modification after manufacture of a mask ROM component, embodiments of flexible ROM storage (“FRS”) systems and methods use a closely coupled one-time programmable (“OTP”) memory component to store modified instructions and/or data. Advantageously, because the OTP memory component may be manufactured “blank” and programmed at a later time, modifications to code and/or data stored in an unchangeable mask ROM may be accomplished via pointers in fuses of a security controller that branch the request to the OTP and bypass the mask ROM.

Abstract translation: 公开了用于便携式计算设备（“PCD”）中的编码指令的灵活的只读存储器（“ROM”）存储的方法和系统的各种实施例。 由于与主引导加载程序（“PBL”）相关联的某些指令和/或数据在制造掩模ROM组件之后可能是有缺陷的或需要修改的，所以灵活的ROM存储（“FRS”）系统和方法的实施例使用紧密的 耦合的一次性可编程（“OTP”）存储器组件来存储经修改的指令和/或数据。 有利地，因为OTP存储器组件可以在稍后的时间被制造为“空白”并被编程，所以可以通过安全控制器的熔丝中的指针来实现对不可改变的掩模ROM中存储的代码和/或数据的修改，该安全控制器的熔丝将该请求分配到 OTP并绕过掩模ROM。