公开(公告)号：US20170004034A1

公开(公告)日：2017-01-05

申请号：US14791352

申请日：2015-07-03

Applicant: QUALCOMM INCORPORATED

Inventor： RICHARD ALAN STEWART ,  DEXTER TAMIO CHUN

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246

Abstract: Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array.

Abstract translation: 公开了用于提供具有闪存单元映射的错误检测或校正的系统，方法和计算机程序。 一个实施例是一种方法，包括为闪存设备的主阵列中的物理页生成原始页数据。 原始页数据包括使用非二功能闪存单元映射生成的物理页面的容量小于该容量。 使用错误检测或校正方案为原始页数据生成一个或多个奇偶校验位。 该方法将原始页面数据和一个或多个奇偶校验位存储在主阵列中的物理页面中。

公开(公告)号：US20160224080A1

公开(公告)日：2016-08-04

申请号：US14697590

申请日：2015-04-27

Applicant: QUALCOMM INCORPORATED

Inventor： RICHARD ALAN STEWART

IPC: G06F1/20 ,  G05B13/02

CPC classification number: G06F1/206 ,  G05B13/021 ,  G11C7/04 ,  G11C29/028 ,  G11C2207/2254

Abstract: Various embodiments of methods and systems for calibration margin optimization of a target component in a portable computing device are disclosed. Because calibration of certain components is most optimally implemented when the component is at a certain operating temperature, or a series of certain operating temperatures, embodiments of the solution leverage thermal energy generation capabilities of nearby components to manage the operating temperature of a target component to be calibrated.

Abstract translation: 公开了用于便携式计算设备中的目标组件的校准余量优化的方法和系统的各种实施例。 因为某些组件的校准在组件处于某一工作温度或一系列某些工作温度时最佳地实现，因此该解决方案的实施例利用了附近组件的热能产生能力来管理目标组件的工作温度为 校准。

公开(公告)号：US20170220412A1

公开(公告)日：2017-08-03

申请号：US15489621

申请日：2017-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： RICHARD ALAN STEWART ,  DEXTER TAMIO CHUN

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246

Abstract: Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array.

公开(公告)号：US20160239442A1

公开(公告)日：2016-08-18

申请号：US14622017

申请日：2015-02-13

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  RICHARD ALAN STEWART ,  SUBRATO KUMAR DE

IPC: G06F13/26 ,  G06F13/18

CPC classification number: G06F13/26 ,  G06F13/1636 ,  G06F13/1663 ,  G06F13/18

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing a signal to each of a plurality of processors on a system on chip (SoC) for scheduling the maintenance event; each of the plurality of processors independently generating in response to the signal a corresponding schedule notification for the maintenance event; and the memory controller determining when to execute the maintenance event in response to receiving one or more of the schedule notifications generated by the plurality of processors and based on a processor priority scheme.

Abstract translation: 公开了用于调度易失性存储器维护事件的系统，方法和计算机程序。 一个实施例是一种方法，包括：存储器控制器，其确定用于经由存储器数据接口耦合到存储器控制器的易失性存储器设备执行维护事件的服务时间（ToS）窗口; 所述存储器控制器为片上系统（SoC）上的多个处理器中的每一个提供信号，用于调度所述维护事件; 所述多个处理器中的每一个独立地响应于所述信号产生用于所述维护事件的对应的调度通知; 并且所述存储器控制器响应于接收到由所述多个处理器产生的所述调度通知中的一个或多个并且基于处理器优先级方案来确定何时执行所述维护事件。