公开(公告)号：US10585734B2

公开(公告)日：2020-03-10

申请号：US16223364

申请日：2018-12-18

Applicant: QUALCOMM Incorporated

Inventor： James Lionel Panian ,  Derek Rohde

IPC: G06F11/07 ,  G06F12/0831 ,  G06F12/1081 ,  G06F12/1027 ,  G06F13/42

Abstract: Fast invalidation in peripheral component interconnect (PCI) express (PCIe) address translation services (ATS) initially utilize a fast invalidation request to alert endpoints that an address is being invalidated with a fast invalidation synchronization command that causes the endpoints to flush through any residual read/write commands associated with any invalidated address and delete any associated address entries in an address translation cache (ATC). Each endpoint may send a synchronization complete acknowledgement to the host. Further, a tag having an incrementing identifier for each invalidation request may be used to determine if an endpoint has missed an invalidation request.

公开(公告)号：US20190205278A1

公开(公告)日：2019-07-04

申请号：US16223364

申请日：2018-12-18

Applicant: QUALCOMM Incorporated

Inventor： James Lionel Panian ,  Derek Rohde

IPC: G06F13/42

Abstract: Fast invalidation in peripheral component interconnect (PCI) express (PCIe) address translation services (ATS) initially utilize a fast invalidation request to alert endpoints that an address is being invalidated with a fast invalidation synchronization command that causes the endpoints to flush through any residual read/write commands associated with any invalidated address and delete any associated address entries in an address translation cache (ATC). Each endpoint may send a synchronization complete acknowledgement to the host. Further, a tag having an incrementing identifier for each invalidation request may be used to determine if an endpoint has missed an invalidation request.

公开(公告)号：US10310585B2

公开(公告)日：2019-06-04

申请号：US15726566

申请日：2017-10-06

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg ,  Richard Dominic Wietfeldt

IPC: G06F1/32 ,  G06F13/42 ,  G06F1/3234 ,  G06F13/40 ,  H01L23/29 ,  H04L12/931

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

公开(公告)号：US20180120921A1

公开(公告)日：2018-05-03

申请号：US15726566

申请日：2017-10-06

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg ,  Richard Dominic Wietfeldt

IPC: G06F1/32 ,  G06F13/40 ,  H04L12/931 ,  H01L23/29

CPC classification number: G06F1/3253 ,  G06F13/4072 ,  G06F13/4273 ,  G06F13/4291 ,  H01L23/291 ,  H04L49/40 ,  Y02D10/151

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

公开(公告)号：US09933834B2

公开(公告)日：2018-04-03

申请号：US14864586

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  James Lionel Panian

IPC: G06F1/26 ,  G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F13/4286 ,  G06F13/4295

Abstract: A dual-data-rate interface is provided that includes a transmitter driving a transmit pin coupled to a receive pin of a receiver. The receiver drives its receive pin with cycles of a fetch clock. The transmitter responds to each edge of the fetch clock by transmitting a bit over the transmit pin to the receiver.

公开(公告)号：US09880965B2

公开(公告)日：2018-01-30

申请号：US14850809

申请日：2015-09-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  James Lionel Panian ,  Radu Pitigoi-Aron

IPC: G06F13/00 ,  G06F13/14 ,  G06F13/20 ,  G06F13/42 ,  G06F1/10 ,  G06F13/38

CPC classification number: G06F13/4221 ,  G06F1/10 ,  G06F13/385

Abstract: A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.

公开(公告)号：US20160077995A1

公开(公告)日：2016-03-17

申请号：US14850809

申请日：2015-09-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  James Lionel Panian ,  Radu Pitigoi-Aron

IPC: G06F13/42 ,  G06F1/10

CPC classification number: G06F13/4221 ,  G06F1/10 ,  G06F13/385

Abstract: A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.

Abstract translation: 提供了一个从处理器接收GPIO信号发送组件的虚拟GPIO接口。 虚拟GPIO接口以传统方式通过GPIO引脚传输GPIO信号发送组的一部分。 然而，虚拟GPIO接口将GPIO信号发送组的剩余部分提供给有限状态机，将剩余部分中的GPIO信号序列化为虚拟GPIO信号帧。 一个经过修改的UART接口可以响应UART过采样时钟的周期，通过UART发送引脚发送帧。