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    Negative current sense feedback for reverse boost mode
    25.
    发明授权
    Negative current sense feedback for reverse boost mode 有权
    反向升压模式的负电流检测反馈

    公开(公告)号：US09442503B2

    公开(公告)日：2016-09-13

    申请号：US13752197

    申请日：2013-01-28

    Applicant: QUALCOMM Incorporated

    Inventor： Joseph D Rutkowski ,  Lennart Karl-Axel Mathe

    IPC: G05F1/00 ,  G05F1/618 ,  H02M3/156 ,  H02M1/00

    CPC classification number: G05F1/618 ,  H02M3/156 ,  H02M3/1563 ,  H02M2001/0009

    Abstract: Techniques for providing negative current information to a control loop for a buck converter in reverse boost mode. In an aspect, negative as well as positive current through an inductor is sensed and provided to adjust a ramp voltage in the control loop for the buck converter. The techniques may prevent current through the inductor during reverse boost mode from becoming increasingly negative without bound; the techniques thereby reduce settling times when the target output voltage is reduced from a first level to a second level. In an aspect, the negative current sensing may be provided by sensing negative current through a charging, or PMOS, switch of the buck converter. The sensed negative current may be subtracted from a current used to generate the ramp voltage.

    Abstract translation: 用于以反向升压模式向降压转换器的控制回路提供负电流信息的技术。 在一个方面，检测并提供通过电感器的负电流和正电流以调整用于降压转换器的控制回路中的斜坡电压。 这些技术可以防止在反向升压模式期间通过电感器的电流在没有限制的情况下变得越来越负; 因此当目标输出电压从第一电平降低到第二电平时，这些技术可以减少稳定时间。 在一方面，负电流感测可以通过感测通过降压转换器的充电或PMOS开关的负电流来提供。 感测到的负电流可以从用于产生斜坡电压的电流中减去。

    Noise shaping for switching circuitry
    26.
    发明授权
    Noise shaping for switching circuitry 有权
    开关电路的噪声整形

    公开(公告)号：US09059793B2

    公开(公告)日：2015-06-16

    申请号：US13752159

    申请日：2013-01-28

    Applicant: QUALCOMM Incorporated

    Inventor： Song S Shi ,  Lennart Karl-Axel Mathe ,  Liang Dai

    IPC: G05F1/00 ,  H04B15/00 ,  G05F1/10 ,  H02M1/12 ,  H02M1/44 ,  H02M3/156 ,  H03F3/217 ,  H03F1/02

    CPC classification number: H04B15/00 ,  G05F1/10 ,  H02M1/12 ,  H02M1/44 ,  H02M3/156 ,  H03F1/0211 ,  H03F3/217 ,  H03F2200/432

    Abstract: Techniques for creating one or more notch frequencies in the power density spectrum of an output voltage generated by switching circuitry. In an aspect, high- and low-side switches are coupled to an output voltage via an inductor. The spectral power of the output voltage at one or more frequencies is estimated, and the estimated spectral power is provided to a switch controller controlling the switches. The switch controller may be configured to switch the switches only in response to detecting that the estimated spectral power at the notch frequency is at a minimum. In certain exemplary aspects, the techniques may be incorporated in an envelope-tracking system, wherein the switching circuitry forms part of a switched-mode power supply (SMPS) supplying low-frequency power to a power amplifier load.

    Abstract translation: 在由开关电路产生的输出电压的功率密度谱中产生一个或多个陷波频率的技术。 在一个方面，高侧和低侧开关通过电感耦合到输出电压。 估计在一个或多个频率处的输出电压的频谱功率，并且将估计的频谱功率提供给控制开关的开关控制器。 开关控制器可以被配置为仅响应于检测到陷波频率处的估计频谱功率为最小而切换开关。 在某些示例性方面，这些技术可以并入包络跟踪系统中，其中开关电路形成向功率放大器负载提供低频功率的开关模式电源（SMPS）的一部分。

    SENSOR ARRAY WITH RECEIVER BIAS ELECTRODE
    27.
    发明申请
    SENSOR ARRAY WITH RECEIVER BIAS ELECTRODE 有权
    传感器阵列与接收器偏置电极

    公开(公告)号：US20150016223A1

    公开(公告)日：2015-01-15

    申请号：US14332242

    申请日：2014-07-15

    Applicant: QUALCOMM Incorporated

    Inventor： Timothy Dickinson ,  Lennart Karl-Axel Mathe ,  Scott McCarthy ,  Kostadin Dimitrov Djordjev ,  Louis Dominic Oliveira ,  Qubo Zhou

    IPC: G01S15/02

    CPC classification number: G06F3/043 ,  G01H1/04 ,  G01S15/02 ,  G06F3/0416 ,  G06F3/0436

    Abstract: A method of operation of an ultrasonic sensor array includes receiving a receiver bias voltage at a receiver bias electrode of the ultrasonic sensor array to bias piezoelectric sensor elements of the ultrasonic sensor array. The method further includes receiving a transmitter control signal at the ultrasonic sensor array to cause an ultrasonic transmitter of the ultrasonic sensor array to generate an ultrasonic wave. The method further includes generating data samples based on a reflection of the ultrasonic wave. The receiver bias voltage and the transmitter control signal are received from an integrated circuit that is coupled to the ultrasonic sensor array.

    Abstract translation: 超声波传感器阵列的操作方法包括在超声波传感器阵列的接收器偏置电极处接收接收器偏置电压，以偏压超声波传感器阵列的压电传感器元件。 该方法还包括在超声波传感器阵列处接收发射器控制信号以使超声波传感器阵列的超声波发射器产生超声波。 该方法还包括基于超声波的反射生成数据样本。 接收器偏置电压和发射机控制信号从耦合到超声波传感器阵列的集成电路接收。

    METHOD AND INTEGRATED CIRCUIT FOR OPERATING A SENSOR ARRAY
    28.
    发明申请
    METHOD AND INTEGRATED CIRCUIT FOR OPERATING A SENSOR ARRAY 审中-公开
    用于操作传感器阵列的方法和集成电路

    公开(公告)号：US20150015515A1

    公开(公告)日：2015-01-15

    申请号：US14332267

    申请日：2014-07-15

    Applicant: QUALCOMM Incorporated

    Inventor： Timothy Dickinson ,  Lennart Karl-Axel Mathe ,  Scott McCarthy ,  Kostadin Dimitrov Djordjev ,  Louis Dominic Oliveira ,  Qubo Zhou

    IPC: G06F3/043 ,  G01H1/04

    CPC classification number: G06F3/043 ,  G01H1/04 ,  G01S15/02 ,  G06F3/0416 ,  G06F3/0436

    Abstract: An apparatus includes an integrated circuit configured to be operatively coupled to a sensor array that is configured to generate an ultrasonic wave. The integrated circuit includes a transmitter circuit configured to provide a first signal to the sensor array. The integrated circuit further includes a receiver circuit configured to receive a second signal from the sensor array in response to providing the first signal. The sensor array includes an ultrasonic transmitter configured to generate the ultrasonic wave in response to the first signal and a piezoelectric receiver layer configured to detect a reflection of the ultrasonic wave.

    Abstract translation: 一种装置包括被配置为可操作地耦合到被配置为产生超声波的传感器阵列的集成电路。 集成电路包括被配置为向传感器阵列提供第一信号的发射器电路。 集成电路还包括接收器电路，其被配置为响应于提供第一信号而从传感器阵列接收第二信号。 传感器阵列包括响应于第一信号产生超声波的超声波发射器和被配置为检测超声波的反射的压电接收层。

    Boost converter control for envelope tracking
    29.
    发明授权
    Boost converter control for envelope tracking 有权
    升压转换器控制用于包络跟踪

    公开(公告)号：US08754707B2

    公开(公告)日：2014-06-17

    申请号：US13659667

    申请日：2012-10-24

    Applicant: QUALCOMM Incorporated

    Inventor： Lennart Karl-Axel Mathe ,  Song S Shi ,  Yunfei Shi

    IPC: H03G3/20

    CPC classification number: H03F1/0238 ,  H03F2200/102 ,  H03F2200/435

    Abstract: Techniques for controlling boost converter operation in an envelope tracking (ET) system. In an aspect, an enable generation block is provided to generate an enable signal for a boost converter, wherein the enable signal is turned on in response to detecting that a sum of a first headroom voltage and an enable peak of a tracking supply voltage is greater than an amplifier supply voltage of the ET system. The enable signal may be turned on for a predetermined enable on duration. In another aspect, a target generation block is provided to generate a target voltage for the boost converter, wherein the target voltage comprises the sum of a second headroom voltage and a target peak of the tracking supply voltage.

    Abstract translation: 用于控制包络跟踪（ET）系统中升压转换器操作的技术。 在一方面中，提供使能生成块以产生用于升压转换器的使能信号，其中响应于检测到第一余量电压和跟踪电源电压的使能峰值之和更大而导通使能信号 比ET系统的放大器电源电压高。 使能信号可以接通预定使能持续时间。 在另一方面，提供目标产生模块以产生升压转换器的目标电压，其中目标电压包括第二余量电压和跟踪电源电压的目标峰值之和。

    Low-power inter-die communication using delay lines
    30.
    发明授权
    Low-power inter-die communication using delay lines 有权

    公开(公告)号：US11695400B1

    公开(公告)日：2023-07-04

    申请号：US17887282

    申请日：2022-08-12

    Applicant: QUALCOMM Incorporated

    Inventor： Sameer Wadhwa ,  Lennart Karl-Axel Mathe

    IPC: H03K5/00 ,  H03K5/14 ,  H03K5/1534 ,  H03K5/19 ,  H03K5/15

    CPC classification number: H03K5/14 ,  H03K5/1534 ,  H03K5/19 ,  H03K5/1504 ,  H03K5/15033

    Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

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