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公开(公告)号：US20230120661A1
公开(公告)日：2023-04-20
申请号：US17965684
申请日：2022-10-13
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Amir Amirkhany , Suresh Rajan , Mohammad Hekmat , Dinesh Patil
IPC: G06F13/16 , G11C7/10 , G11C8/18 , G11C11/419 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C5/02 , G06F13/40
Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号：US20200050561A1
公开(公告)日：2020-02-13
申请号：US16546694
申请日：2019-08-21
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Amir Amirkhany , Suresh Rajan , Mohammad Hekmat , Dinesh Patil
IPC: G06F13/16 , G06F13/40 , G11C7/10 , G11C5/02 , G11C11/4096 , G11C11/4093 , G11C11/4076 , G11C7/22 , G11C11/419 , G11C8/18
Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号：US09722539B2
公开(公告)日：2017-08-01
申请号：US14858965
申请日：2015-09-18
Applicant: Rambus Inc.
Inventor： Mohammad Hekmat , Reza Navid
Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.
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公开(公告)号：US09571034B2
公开(公告)日：2017-02-14
申请号：US15049517
申请日：2016-02-22
Applicant: Rambus Inc.
Inventor： Mohammad Hekmat , Farshid Aryanfar , Kambiz Kaviani
CPC classification number: H03B27/00 , H01F27/006 , H01F27/2804 , H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B15/00 , H03K5/145 , H03K5/24 , H03K2005/00052
Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.
Abstract translation: 耦合多电感及其应用。 一种装置包括几个电路级。 每个电路级包括与其相邻电路级的电感元件重叠的电感元件，形成耦合电路级的回路。 该装置可以是例如具有彼此磁耦合的多个振荡器的多相振荡器，用于在不同相位产生振荡信号。 该装置也可以是例如用于组合输入信号的相位插值器。
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公开(公告)号：US20160190986A1
公开(公告)日：2016-06-30
申请号：US14960065
申请日：2015-12-04
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20140380082A1
公开(公告)日：2014-12-25
申请号：US14482782
申请日：2014-09-10
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
Abstract translation: 描述能够通过使用注入锁定振荡器执行分数时钟倍增的电路。 本文描述的一些实施例通过周期性地改变喷射位置，从喷射信号的一组注入位置周期性地改变喷射位置，和/或通过周期性地改变注入的注入信号的相位相位来改变相位 进入国际劳工组织。
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公开(公告)号：US20140015615A1
公开(公告)日：2014-01-16
申请号：US13925330
申请日：2013-06-24
Applicant: Rambus Inc.
Inventor： Mohammad Hekmat , Reza Navid
IPC: H03L7/06
Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.
Abstract translation: 锁相环电路包括具有多个耦合振荡器的多相振荡器。 校准模块在校准过程中检测锁相环电路中的不同振荡器的频率特性之间的不匹配。 校准模块然后校准各种振荡器以补偿检测到的失配。 一旦校准，尽管不同振荡器之间的频率特性不匹配，锁相环电路可以很少或没有性能下降。
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公开(公告)号：US20210141748A1
公开(公告)日：2021-05-13
申请号：US17081909
申请日：2020-10-27
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Amir Amirkhany , Suresh Rajan , Mohammad Hekmat , Dinesh Patil
IPC: G06F13/16 , G11C7/10 , G11C8/18 , G11C11/419 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C5/02 , G06F13/40
Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号：US09954489B2
公开(公告)日：2018-04-24
申请号：US15632045
申请日：2017-06-23
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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公开(公告)号：US20180019706A1
公开(公告)日：2018-01-18
申请号：US15632045
申请日：2017-06-23
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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