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公开(公告)号：US20170097905A1
公开(公告)日：2017-04-06
申请号：US15333001
申请日：2016-10-24
申请人： Rambus Inc.
CPC分类号： G06F13/1673 , G06F13/4068 , G11C5/02 , G11C7/10 , G11C7/1012 , G11C7/1021 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号：US09501433B2
公开(公告)日：2016-11-22
申请号：US14683080
申请日：2015-04-09
申请人： Rambus Inc.
IPC分类号： G06F13/00 , G06F13/16 , G11C7/10 , G11C8/18 , G11C11/419 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C5/02 , G11C29/02
CPC分类号： G06F13/1673 , G06F13/4068 , G11C5/02 , G11C7/10 , G11C7/1012 , G11C7/1021 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号：US20160072440A1
公开(公告)日：2016-03-10
申请号：US14858965
申请日：2015-09-18
申请人： Rambus Inc.
发明人： Mohammad Hekmat , Reza Navid
摘要： A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.
摘要翻译： 锁相环电路包括具有多个耦合振荡器的多相振荡器。 校准模块在校准过程中检测锁相环电路中的不同振荡器的频率特性之间的不匹配。 校准模块然后校准各种振荡器以补偿检测到的失配。 一旦校准，尽管不同振荡器之间的频率特性不匹配，锁相环电路可以很少或没有性能下降。
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公开(公告)号：US09009400B2
公开(公告)日：2015-04-14
申请号：US14023970
申请日：2013-09-11
申请人： Rambus Inc.
IPC分类号： G06F13/00 , G11C7/10 , G11C8/18 , G11C11/419 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C29/02
CPC分类号： G06F13/1673 , G06F13/4068 , G11C5/02 , G11C7/10 , G11C7/1012 , G11C7/1021 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
摘要翻译： 半导体存储器系统包括第一半导体存储器管芯和第二半导体存储器管芯。 第一半导体存储器管芯包括主数据接口，用于在写操作期间接收输入数据流，并将输入数据流反序列化为第一多个数据流，并且还包括耦合到主数据接口的辅数据接口， 发送第一多个数据流。 第二半导体存储器管芯包括耦合到第一半导体存储器管芯的次级数据接口的次级数据接口，以接收第一多个数据流。
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公开(公告)号：US20240345971A1
公开(公告)日：2024-10-17
申请号：US18629167
申请日：2024-04-08
申请人： Rambus Inc.
IPC分类号： G06F13/16 , G06F13/40 , G11C5/02 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/02
CPC分类号： G06F13/1673 , G06F13/4068 , G11C5/02 , G11C7/10 , G11C7/1012 , G11C7/1021 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号：US10831685B2
公开(公告)日：2020-11-10
申请号：US16546694
申请日：2019-08-21
申请人： Rambus Inc.
IPC分类号： G06F13/16 , G11C7/10 , G11C8/18 , G11C11/419 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C5/02 , G06F13/40 , G11C29/02
摘要： A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号：US10541649B2
公开(公告)日：2020-01-21
申请号：US15638329
申请日：2017-06-29
申请人： Rambus Inc.
发明人： Mohammad Hekmat , Reza Navid
摘要： A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.
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公开(公告)号：US10402352B2
公开(公告)日：2019-09-03
申请号：US15333001
申请日：2016-10-24
申请人： Rambus Inc.
IPC分类号： G06F13/00 , G06F13/16 , G11C7/10 , G11C8/18 , G11C11/419 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C5/02 , G06F13/40 , G11C29/02
摘要： A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号：US09716468B2
公开(公告)日：2017-07-25
申请号：US14960065
申请日：2015-12-04
申请人： Rambus Inc.
发明人： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC分类号： H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
摘要： Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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10.发明授权Data buffer with strobe-based primary interface and a strobe-less secondary interface 有权数据缓冲区，具有基于选通的主接口和无闪光次要接口公开(公告)号：US09417807B2
公开(公告)日：2016-08-16
申请号：US14820207
申请日：2015-08-06
申请人： RAMBUS INC.
发明人： Kambiz Kaviani , Amir Amirkhany , Dinesh Patil , Mohammad Hekmat
CPC分类号： G06F3/0619 , G06F3/0656 , G06F3/0683 , G06F12/0246 , G06F12/0802 , G06F2212/20 , G11C5/04 , G11C7/1066 , G11C7/1093
摘要： A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.
摘要翻译： 描述了具有基于选通脉冲的主界面和在存储器模块上使用的无频闪次要接口的数据缓冲器。 一个存储器模块包括地址缓冲器，数据缓冲器和多个动态随机存取存储器（DRAM）器件。 地址缓冲器通过无闪光次要接口向数据缓冲器和DRAM器件提供定时参考，用于数据缓冲器和DRAM器件之间的一个或多个事务。
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