公开(公告)号：US20140054597A1

公开(公告)日：2014-02-27

申请号：US13910202

申请日：2013-06-05

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour ,  Paul Partyka

IPC: H01L29/20 ,  H01L21/02

CPC classification number: H01L29/2003 ,  H01L21/0254 ,  H01L23/36 ,  H01L29/4175 ,  H01L2224/16 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/00

Abstract: The present disclosure provides a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside.

Abstract translation: 本公开提供了功率器件和功率器件封装。 通常，本公开的功率器件包括管芯背面和管芯前端。 具有设置在其上的外延层的半绝缘基板夹在模具背面和模具前侧之间。 模具前端的垫片与模具背面耦合，图案化的背衬设置在通过半绝缘衬底和外延层从模具背面到模具前端的通孔内。

公开(公告)号：US20140054596A1

公开(公告)日：2014-02-27

申请号：US13871526

申请日：2013-04-26

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L27/0248 ,  H01L29/2003 ,  H01L29/778

Abstract: A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.

Abstract translation: 公开了具有电应力（EOS）保护的半导体器件。 半导体器件包括半绝缘层，设置在半绝缘层上的第一触点和设置在半绝缘层上的第二触点。 钝化层设置在半绝缘层上。 钝化层的绝缘强度大于半绝缘层的绝缘强度，以确保在电压击穿之前在第一接触件和第二接触件之间的半绝缘区域内半绝缘层内发生电压击穿 发生在钝化层中。

公开(公告)号：US20130277687A1

公开(公告)日：2013-10-24

申请号：US13795926

申请日：2013-03-12

Applicant: RF MICRO DEVICES, INC.

Inventor： Kevin Wesley Kobayashi ,  Haldane S. Henry ,  Andrew P. Ritenour

IPC: H01L29/423 ,  H01L29/812

CPC classification number: H01L29/402 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7787 ,  H01L29/80 ,  H01L29/812

Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.