公开(公告)号：US20220224325A1

公开(公告)日：2022-07-14

申请号：US17568637

申请日：2022-01-04

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H03K17/16

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

公开(公告)号：US20220223733A1

公开(公告)日：2022-07-14

申请号：US17547707

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Chun-Lung Chang ,  Chih-Wen Hsiung ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H01L29/78 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well region, a shallow trench isolation region, a drift oxide region, a body region, a gate, a source, and a drain. The drift oxide region is located on a drift region. The shallow trench isolation region is located below the drift oxide region. A part of the drift oxide region is located vertically above a part of the shallow trench isolation region and is in contact with the shallow trench isolation region. The shallow trench isolation region is formed between the drain and the body region.

公开(公告)号：US20210074851A1

公开(公告)日：2021-03-11

申请号：US16868456

申请日：2020-05-06

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chien-Wei Chiu ,  Ta-Yung Yang ,  Wu-Te Weng ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chih-Wen Hsiung ,  Kuo-Chin Chiu ,  Chun-Lung Chang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

Abstract: The present invention provides a high voltage device and a manufacturing method thereof. The high voltage device includes: a semiconductor layer, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, and a drain. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region right above the drift region. The sub-gate is parallel with the gate. A conductive layer of the gate has a first conductivity type, and a conductive layer of the sub-gate has a second conductivity type or is an intrinsic semiconductor structure.