公开(公告)号：US20220165880A1

公开(公告)日：2022-05-26

申请号：US17666501

申请日：2022-02-07

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Kun-Huang Yu ,  Ying-Shiou Lin ,  Chu-Feng Chen ,  Chung-Yu Hung ,  Yi-Rong Tu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.

公开(公告)号：US20210135005A1

公开(公告)日：2021-05-06

申请号：US17148360

申请日：2021-01-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Kun-Huang Yu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L21/265

Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.

公开(公告)号：US11522536B2

公开(公告)日：2022-12-06

申请号：US17568637

申请日：2022-01-04

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

公开(公告)号：US20220336588A1

公开(公告)日：2022-10-20

申请号：US17718101

申请日：2022-04-11

Applicant: Richtek Technology Corporation

Inventor： Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body cofntact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

公开(公告)号：US20220157982A1

公开(公告)日：2022-05-19

申请号：US17506422

申请日：2021-10-20

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Chin Chiu ,  Ta-Yung Yang ,  Chien-Wei Chiu ,  Wu-Te Weng ,  Chien-Yu Chen ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Ting-Wei Liao

IPC: H01L29/78 ,  H01L29/872 ,  H01L29/66

Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.

公开(公告)号：US10923589B2

公开(公告)日：2021-02-16

申请号：US16542268

申请日：2019-08-15

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Kun-Huang Yu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/167 ,  H01L29/36 ,  H01L21/02 ,  H01L21/762 ,  H01L21/265

Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.

公开(公告)号：US11876453B2

公开(公告)日：2024-01-16

申请号：US17560761

申请日：2021-12-23

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H02M3/158 ,  H02M1/38

CPC classification number: H02M3/158 ,  H02M1/385

Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.

公开(公告)号：US20220238727A1

公开(公告)日：2022-07-28

申请号：US17571401

申请日：2022-01-07

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H01L29/866 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: The present invention provides a Zener diode and a manufacturing method thereof. The Zener diode includes: a semiconductor layer, an N-type region, and a P-type region. The N-type region has N-type conductivity, wherein the N-type region is formed in the semiconductor layer beneath an upper surface of the semiconductor layer, and in contact with the upper surface. The P-type region has P-type conductivity, wherein the P-type region is formed in the semiconductor layer and is completely beneath the N-type region, and in contact with the N-type region. The N-type region overlays the entire P-type region. The N-type region has an N-type conductivity dopant concentration, wherein the N-type conductivity dopant concentration is higher than a P-type conductivity dopant concentration of the P-type region.

公开(公告)号：US20220239224A1

公开(公告)日：2022-07-28

申请号：US17567130

申请日：2022-01-02

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H02M3/158 ,  H02M1/08 ,  H03K17/06

Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.

公开(公告)号：US20220239223A1

公开(公告)日：2022-07-28

申请号：US17560761

申请日：2021-12-23

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H02M3/158 ,  H02M1/38

Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.