公开(公告)号：US11522536B2

公开(公告)日：2022-12-06

申请号：US17568637

申请日：2022-01-04

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

公开(公告)号：US20220336588A1

公开(公告)日：2022-10-20

申请号：US17718101

申请日：2022-04-11

Applicant: Richtek Technology Corporation

Inventor： Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body cofntact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

公开(公告)号：US20220157982A1

公开(公告)日：2022-05-19

申请号：US17506422

申请日：2021-10-20

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Chin Chiu ,  Ta-Yung Yang ,  Chien-Wei Chiu ,  Wu-Te Weng ,  Chien-Yu Chen ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Ting-Wei Liao

IPC: H01L29/78 ,  H01L29/872 ,  H01L29/66

Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.

公开(公告)号：US20230197725A1

公开(公告)日：2023-06-22

申请号：US18052950

申请日：2022-11-07

Applicant: Richtek Technology Corporation

Inventor： Wu-Te Weng ,  Chih-Wen Hsiung ,  Ta-Yung Yang

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L27/0928 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/823814

Abstract: An integrated structure of CMOS devices includes: a semiconductor layer, insulation regions, a first high voltage P-type well and a second high voltage P-type well, a first high voltage N-type well and a second high voltage N-type well, a first low voltage P-type well and a second low voltage P-type well, a first low voltage N-type well and a second low voltage N-type well, and eight gates. A CMOS device having an ultra high threshold voltage is formed in ultra high threshold device region; a CMOS device having a high threshold voltage is formed in high threshold device region; a CMOS device having a middle threshold voltage is formed in the middle threshold device region; and a CMOS device having a low threshold voltage is formed in the low threshold device region.

公开(公告)号：US20230045843A1

公开(公告)日：2023-02-16

申请号：US17749071

申请日：2022-05-19

Applicant: Richtek Technology Corporation

Inventor： Yu-Ting Yeh ,  Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/765 ,  H01L29/66

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

公开(公告)号：US20250142873A1

公开(公告)日：2025-05-01

申请号：US18435550

申请日：2024-02-07

Applicant: Richtek Technology Corporation

Inventor： Wu-Te Weng ,  Yi-Rong Tu ,  Ying-Shiou Lin ,  Yong-Zhong Hu

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/40 ,  H01L29/66

Abstract: A depletion type vertical discrete NMOS device includes: an N-type epitaxial layer formed on an N-type substrate, wherein the N-type epitaxial layer has a top surface and a bottom surface opposite to each other; a P-type well formed in the N-type epitaxial layer; a gate formed outside and connected with the N-type epitaxial layer; an N-type source formed in the N-type epitaxial layer and in contact with the P-type well; an N-type drain including a part of the N-type substrate, which is formed outside and under the N-type epitaxial layer; and an N-type region formed and connected between the P-type well and the gate, which provides a channel, such that the N-type source and the N-type drain are electrically connected with each other during conduction operation, whereas, the N-type source and the N-type drain are electrically disconnected from each other during non-conduction operation.

公开(公告)号：US12136650B2

公开(公告)日：2024-11-05

申请号：US17718101

申请日：2022-04-11

Applicant: Richtek Technology Corporation

Inventor： Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L21/74 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body contact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

公开(公告)号：US20240297067A1

公开(公告)日：2024-09-05

申请号：US18664656

申请日：2024-05-15

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/7621 ,  H01L21/76221 ,  H01L21/76281 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US12062570B2

公开(公告)日：2024-08-13

申请号：US17547829

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/7621 ,  H01L21/76221 ,  H01L21/76281 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US20230197730A1

公开(公告)日：2023-06-22

申请号：US18052062

申请日：2022-11-02

Applicant: Richtek Technology Corporation

Inventor： Wu-Te Weng ,  Chih-Wen Hsiung ,  Ta-Yung Yang

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0928 ,  H01L29/7816 ,  H01L21/823878 ,  H01L29/66681

Abstract: A high voltage complementary metal oxide semiconductor (CMOS) device includes: a semiconductor layer, plural insulation regions, a first N-type high voltage well and a second N-type high voltage well, which are formed by one same ion implantation process, a first P-type high voltage well and a second P-type high voltage well, which are formed by one same ion implantation process, a first drift oxide region and a second oxide region, which are formed by one same etching process by etching a drift oxide layer; a first gate and a second gate, which are formed by one same etching process by etching a polysilicon layer, an N-type source and an N-type drain, and a P-type source and a P-type drain.