公开(公告)号：US20220336441A1

公开(公告)日：2022-10-20

申请号：US17702702

申请日：2022-03-23

Applicant: Richtek Technology Corporation

Inventor： Kuo-Chin Chiu ,  Chien-Wei Chiu

IPC: H01L27/02 ,  H01L21/8234

Abstract: A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.

公开(公告)号：US11522536B2

公开(公告)日：2022-12-06

申请号：US17568637

申请日：2022-01-04

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

公开(公告)号：US20220157982A1

公开(公告)日：2022-05-19

申请号：US17506422

申请日：2021-10-20

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Chin Chiu ,  Ta-Yung Yang ,  Chien-Wei Chiu ,  Wu-Te Weng ,  Chien-Yu Chen ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Ting-Wei Liao

IPC: H01L29/78 ,  H01L29/872 ,  H01L29/66

Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.

公开(公告)号：US20160380093A1

公开(公告)日：2016-12-29

申请号：US15260599

申请日：2016-09-09

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chien-Wei Chiu

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/10 ,  H01L23/535 ,  H01L29/08 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L23/481 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0843 ,  H01L29/1004 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/66212 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/66333 ,  H01L29/66462 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

Abstract translation: 本发明公开了一种立式半导体器件及其制造方法。 所述垂直半导体器件包括：具有第一表面和第二表面的衬底，所述衬底包括由穿过所述衬底的多个导电插塞形成的导电阵列; 形成在所述第一表面上的半导体层，所述半导体层具有第三表面和第四表面，其中所述第四表面面向所述第一表面; 形成在第三表面上的第一电极; 以及形成在所述第二表面上用于电连接到所述导电阵列的第二电极。

公开(公告)号：US12107160B2

公开(公告)日：2024-10-01

申请号：US17726515

申请日：2022-04-21

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng ,  Chien-Wei Chiu

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76202 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66681

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

公开(公告)号：US11961833B2

公开(公告)日：2024-04-16

申请号：US17702702

申请日：2022-03-23

Applicant: Richtek Technology Corporation

Inventor： Kuo-Chin Chiu ,  Chien-Wei Chiu

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/761

CPC classification number: H01L27/0255 ,  H01L21/823481 ,  H01L27/0288 ,  H01L21/761

Abstract: A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.

公开(公告)号：US11876453B2

公开(公告)日：2024-01-16

申请号：US17560761

申请日：2021-12-23

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H02M3/158 ,  H02M1/38

CPC classification number: H02M3/158 ,  H02M1/385

Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.

公开(公告)号：US20220376110A1

公开(公告)日：2022-11-24

申请号：US17726515

申请日：2022-04-21

Applicant: Richtek Technology Corporation

Inventor： Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng ,  Chien-Wei Chiu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L29/66

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

公开(公告)号：US20220238727A1

公开(公告)日：2022-07-28

申请号：US17571401

申请日：2022-01-07

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H01L29/866 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: The present invention provides a Zener diode and a manufacturing method thereof. The Zener diode includes: a semiconductor layer, an N-type region, and a P-type region. The N-type region has N-type conductivity, wherein the N-type region is formed in the semiconductor layer beneath an upper surface of the semiconductor layer, and in contact with the upper surface. The P-type region has P-type conductivity, wherein the P-type region is formed in the semiconductor layer and is completely beneath the N-type region, and in contact with the N-type region. The N-type region overlays the entire P-type region. The N-type region has an N-type conductivity dopant concentration, wherein the N-type conductivity dopant concentration is higher than a P-type conductivity dopant concentration of the P-type region.

公开(公告)号：US20220239224A1

公开(公告)日：2022-07-28

申请号：US17567130

申请日：2022-01-02

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H02M3/158 ,  H02M1/08 ,  H03K17/06

Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.