公开(公告)号：US20220336588A1

公开(公告)日：2022-10-20

申请号：US17718101

申请日：2022-04-11

Applicant: Richtek Technology Corporation

Inventor： Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body cofntact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

公开(公告)号：US20220157982A1

公开(公告)日：2022-05-19

申请号：US17506422

申请日：2021-10-20

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Chin Chiu ,  Ta-Yung Yang ,  Chien-Wei Chiu ,  Wu-Te Weng ,  Chien-Yu Chen ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Ting-Wei Liao

IPC: H01L29/78 ,  H01L29/872 ,  H01L29/66

Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.

公开(公告)号：US20220223733A1

公开(公告)日：2022-07-14

申请号：US17547707

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Chun-Lung Chang ,  Chih-Wen Hsiung ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H01L29/78 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well region, a shallow trench isolation region, a drift oxide region, a body region, a gate, a source, and a drain. The drift oxide region is located on a drift region. The shallow trench isolation region is located below the drift oxide region. A part of the drift oxide region is located vertically above a part of the shallow trench isolation region and is in contact with the shallow trench isolation region. The shallow trench isolation region is formed between the drain and the body region.

公开(公告)号：US20210074851A1

公开(公告)日：2021-03-11

申请号：US16868456

申请日：2020-05-06

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chien-Wei Chiu ,  Ta-Yung Yang ,  Wu-Te Weng ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chih-Wen Hsiung ,  Kuo-Chin Chiu ,  Chun-Lung Chang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

Abstract: The present invention provides a high voltage device and a manufacturing method thereof. The high voltage device includes: a semiconductor layer, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, and a drain. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region right above the drift region. The sub-gate is parallel with the gate. A conductive layer of the gate has a first conductivity type, and a conductive layer of the sub-gate has a second conductivity type or is an intrinsic semiconductor structure.

公开(公告)号：US12136650B2

公开(公告)日：2024-11-05

申请号：US17718101

申请日：2022-04-11

Applicant: Richtek Technology Corporation

Inventor： Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L21/74 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body contact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

公开(公告)号：US20240297067A1

公开(公告)日：2024-09-05

申请号：US18664656

申请日：2024-05-15

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/7621 ,  H01L21/76221 ,  H01L21/76281 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US12062570B2

公开(公告)日：2024-08-13

申请号：US17547829

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/7621 ,  H01L21/76221 ,  H01L21/76281 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US20220223464A1

公开(公告)日：2022-07-14

申请号：US17547829

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.