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21.发明授权Multi-node data processing system and communication protocol in which a stomp signal is propagated to cancel a prior request 失效多节点数据处理系统和传播踩踏信号以消除先前请求的通信协议公开(公告)号：US06519665B1
公开(公告)日：2003-02-11
申请号：US09436900
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F15/16
摘要： A data processing system includes at least first and second nodes and a segmented interconnect having coupled first and second segments. The first node includes the first segment and first and second agents coupled to the first segment, and the second node includes the second segment and a third agent coupled to the second segment. The first node further includes cancellation logic that, in response to the first agent issuing a request on the segmented interconnect that propagates from the first segment to the second segment and the second agent indicating ability to service the request, sends a cancellation message to the third agent instructing the third agent to ignore the request.
摘要翻译： 数据处理系统至少包括第一和第二节点以及具有耦合的第一和第二段的分段互连。 第一节点包括第一段和耦合到第一段的第一和第二代理，并且第二节点包括第二段和耦合到第二段的第三代理。 第一节点还包括消除逻辑，响应于第一代理在从第一段传播到第二段的分段互连上发出请求，并且第二代理指示服务该请求的能力，向第三代发送取消消息 代理指示第三代理人忽略该请求。
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公开(公告)号：US06449691B1
公开(公告)日：2002-09-10
申请号：US09364285
申请日：1999-07-30
IPC分类号： G06F1300
CPC分类号： G06F12/0846 , G06F12/0607 , G06F12/0848 , G06F12/0864 , G06F12/0897
摘要： A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, have diverse cache hardware and each preferably store only data having associated addresses within a respective one of a plurality of subsets of an address space. The diverse cache hardware can include, for example, differing cache sizes, differing associativities, differing sectoring, and differing inclusivities.
摘要翻译： 处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和在同一级别的多个高速缓存。 存储由执行单元使用的数据的高速缓存具有不同的高速缓存硬件，并且每个高速缓存优选仅存储具有地址空间的多个子集中的相应地址内的相关联的地址的数据。 不同的高速缓存硬件可以包括例如不同的高速缓存大小，不同的相关性，不同的扇区和不同的包容性。
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23.发明授权Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response 失效多节点数据处理系统和使用从组合响应获得的目的地ID来路由写入数据的通信协议公开(公告)号：US06848003B1
公开(公告)日：2005-01-25
申请号：US09436901
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F15/16 , G06F15/173
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A data processing system includes a plurality of nodes, which each contain at least one agent and each have an associated node identifier, and memory distributed among the plurality of nodes. The data processing system further includes an interconnect containing a segmented data channel, where each node contains a segment of the segmented data channel and each segment is coupled to at least one other segment by destination logic. In response to snooping a write request of a master agent on the interconnect, a target agent that will service the write request places its node identifier in a snoop response. When the master agent receives the combined response, which contains the node identifier of the target agent, the master agent issues on the segmented data channel a write data transaction specifying the node identifier of the target agent as a destination identifier. In response to receipt of the write data transaction, the destination logic transmits the write data transaction to a next segment only if the destination identifier does not match a node identifier associated with a node containing a current segment.
摘要翻译： 数据处理系统包括多个节点，每个节点包含至少一个代理，并且每个节点都具有相关联的节点标识符，以及分布在多个节点之间的存储器。 数据处理系统还包括一个包含分段数据信道的互连，其中每个节点包含分段数据信道的一个段，并且每个段通过目的地逻辑耦合到至少一个其它段。 响应于在互连上窥探主代理的写请求，将服务于写请求的目标代理将其节点标识符置于窥探响应中。 当主代理接收到包含目标代理的节点标识符的组合响应时，主代理在分段数据信道上发出指定目标代理的节点标识符的写数据事务作为目的地标识符。 响应于写入数据事务的接收，目的地逻辑仅在目的地标识符与与包含当前段的节点相关联的节点标识符不匹配时才将写入数据事务发送到下一个段。
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公开(公告)号：US06598118B1
公开(公告)日：2003-07-22
申请号：US09364284
申请日：1999-07-30
IPC分类号： G60F1200
CPC分类号： G06F12/0864
摘要： A processor having a hashed and partitioned storage subsystem includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a cache subsystem including a plurality of caches that store data utilized by the execution unit. Each cache among the plurality of caches stores only data having associated addresses within a respective one of a plurality of subsets of an address space. In one preferred embodiment, the execution units of the processor include a number of load-store units (LSUs) that each process only instructions that access data having associated addresses within a respective one of the plurality of address subsets. The processor may further be incorporated within a data processing system having a number of interconnects and a number of sets of system memory hardware that each have affinity to a respective one of the plurality of address subsets.
摘要翻译： 具有散列和分区存储子系统的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和包括存储由执行单元使用的数据的多个高速缓存的高速缓存子系统。 多个高速缓存中的每个高速缓存仅存储具有地址空间的多个子集中的相应地址内的相关地址的数据。 在一个优选实施例中，处理器的执行单元包括多个加载存储单元（LSU），每个加载存储单元仅处理访问在多个地址子集中的相应一个地址子集内具有相关联地址的数据的指令。 处理器还可以并入具有多个互连的数据处理系统和多个系统存储器硬件的集合，每个系统存储器硬件各自对多个地址子集中的相应一个具有亲和力。
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25.发明授权公开(公告)号：US06516404B1
公开(公告)日：2003-02-04
申请号：US09364283
申请日：1999-07-30
IPC分类号： G06F1200
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/30138 , G06F9/3016 , G06F9/384 , G06F12/06 , G06F12/0846
摘要： A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of registers coupled to the execution unit. The plurality of registers are partitioned into a plurality of groups, such that registers within each group can store only data having associated addresses within a respective one of a plurality of subsets of an address space.
摘要翻译： 具有散列和分区寄存器文件的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和耦合到执行单元的多个寄存器。 多个寄存器被划分成多个组，使得每个组中的寄存器可以仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据。
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26.发明授权Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response 失效多节点数据处理系统和队列管理方法，其中响应于部分组合响应推测性地取消排队操作公开(公告)号：US06591307B1
公开(公告)日：2003-07-08
申请号：US09436897
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F112
CPC分类号： G06F12/0815 , G06F12/0813 , G06F12/0831
摘要： A data processing system includes an interconnect, a plurality of nodes coupled to the interconnect that each include at least one agent, response logic within each node, and a queue. In response to snooping a transaction on the interconnect, each agent outputs a snoop response. In addition, the queue, which has an associated agent, allocates an entry to service the transaction. The response logic within each node accumulates a partial combined response of its node and any preceding node until a complete combined response for all of the plurality of nodes is obtained. However, prior to the associated agent receiving the complete combined response, the queue speculatively deallocates the entry if the partial combined response indicates that an agent other than the associated agent will service the transaction.
摘要翻译： 数据处理系统包括互连，耦合到互连的多个节点，每个节点包括至少一个代理，每个节点内的响应逻辑和队列。 响应在互连上窥探事务，每个代理输出一个侦听响应。 此外，具有关联代理的队列分配一个条目来为事务提供服务。 每个节点内的响应逻辑累积其节点和任何先前节点的部分组合响应，直到获得所有多个节点的完整组合响应。 然而，在相关联的代理接收到完整的组合响应之前，如果部分组合响应指示除了相关联的代理之外的代理将服务于该事务，则队列推测性地释放该条目。
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27.发明授权Processor assigning data to hardware partition based on selectable hash of data address 失效处理器根据数据地址的可选哈希分配数据到硬件分区公开(公告)号：US06470442B1
公开(公告)日：2002-10-22
申请号：US09364286
申请日：1999-07-30
IPC分类号： B06F1576
CPC分类号： G06F9/3891 , G06F9/3012 , G06F9/3013 , G06F9/3802 , G06F9/384 , G06F9/3885 , G06F15/7857
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing data. The data processed by each hardware partition is assigned according to a selectable hash of addresses associated as with the data. In a preferred embodiment, the selectable hash can be altered dynamically during the operation of the processor, for example, in response to detection of an error or a load imbalance between the hardware partitions.
摘要翻译： 处理器包括执行资源，数据存储和指令排序单元，其耦合到执行资源和数据存储器，其将数据存储器内的指令提供给执行资源。 执行资源，数据存储和指令排序单元中的至少一个用多个用于处理数据的相同功能的硬件分区来实现。 由每个硬件分区处理的数据根据与数据相关联的地址的可选择的散列来分配。 在优选实施例中，可以在处理器的操作期间动态地改变可选择的散列，例如响应于硬件分区之间的错误或负载不平衡的检测。
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公开(公告)号：US06662275B2
公开(公告)日：2003-12-09
申请号：US09782578
申请日：2001-02-12
IPC分类号： G06F1208
CPC分类号： G06F12/0811 , G06F12/0848
摘要： A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.
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29.发明授权公开(公告)号：US06629214B1
公开(公告)日：2003-09-30
申请号：US09437186
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1300
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3857
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized. In particular, the claimed system and method provides that a given processor, after acquiring a lock or reservation to a given cache line, will keep the lock, to make successive modifications to the cache line, instead of releasing it to other processors after making only one modification. By doing so, the overhead typically required to acquire a lock before making any cache line modification is eliminated for successive modifications.
摘要翻译： 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的传统系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。 额外的缓存状态允许优化缓存状态转换序列。 特别地，所要求保护的系统和方法规定，给定的处理器在获得对给定高速缓存行的锁定或预留之后将保持锁定以对缓存行进行连续修改，而不是在仅进行制作之后将其释放到其他处理器 一个修改。 通过这样做，为了连续修改，消除了在进行任何高速缓存行修改之前获取锁的通常需要的开销。
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30.发明授权公开(公告)号：US06553462B2
公开(公告)日：2003-04-22
申请号：US09753057
申请日：2000-12-28
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line. Partial intervention may be achieved by issuing a request to retrieve an entire cache line, and sourcing only a first sector of the cache line in response to the request. A second sector of the same cache line may be sourced from a third cache. Other sectors may also be sourced from a system memory device of the computer system as well. Appropriate system bus codes are utilized to transmit cache operations to the system bus and indicate which sectors of the cache line are targets of the cache operation.
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