Abstract:
A control circuit of a power converter includes: an input signal detection circuit, configured to operably detect a magnitude of an input signal to generate a detection signal; a clock generation circuit, configured to operably generate a clock signal; an error detection circuit, configured to operably generate an error signal according to a reference signal and a feedback signal; a control signal generation circuit, coupled with the clock generation circuit and the error detection circuit, configured to operably control a switching frequency of a power switch according to the clock signal and the error signal; and a reverse adjusting circuit, coupled with the input signal detection circuit, configured to operably adjust the clock generation circuit or the control signal generation circuit according to the detection signal to configure the switching frequency of the power switch to be inversely proportional to the magnitude of the input signal.
Abstract:
An apparatus and a method for implementing a multiple function pin in a boundary conduction mode power supply, uses a same pin to switch a power switch and to achieve zero current detection to reduce pin count and save cost of a control integrated circuit. A first voltage is applied to the multiple function pin to turn on the power switch, and then a second voltage is applied to the multiple function pin after the power switch has been turned on for a first time, to thereby turn off the power switch. After the power switch has been turned off for a second time, a third voltage is applied to the multiple function pin keep the power switch off. Preferably, a tristate output driver is used to provide the first and second voltages, and a clamping circuit is used to provide the third voltage.
Abstract:
A control circuit for a power converter has a current source, a sampling circuit, a signal processing circuit, a driving circuit, and a shared pin. The shared pin is used for coupling with a resistor and a switch. The current source, coupled with the shared pin, provides a current through the shared pin to the resistor in a first period. The sampling circuit, coupled with the shared pin, samples signals on the shared pin for generating a first sampling value and a second sampling value. The signal processing circuit, coupled with the sampling circuit, compares the first sampling value and the second sampling value. The driving circuit generates driving signals for conducting the switch. When the difference of the first sampling value and the second sampling value is less than a predetermined value, the signal processing circuit configures the driving circuit to intermittently conduct the switch in a second period.
Abstract:
A floating gate driver includes a level shifter to transmit a set signal and a reset signal to a first output terminal and a second output terminal, respectively. The level shifter includes a first high-voltage transistor, a first current limiter and a first input transistor connected in series between the first output terminal and a ground terminal, and a second high-voltage transistor, a second current limiter and a second input transistor connected in series between the second output terminal and the ground terminal, and the first and second high-voltage transistors are remained on. With this arrangement, the level shifter can transmit signals from low side to high side under better safe operating area and has better noise immunity.