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21.发明授权Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell 有权在双栅极CMOS工艺中形成多电平ROM存储器的方法以及相应的ROM存储单元公开(公告)号：US06521957B2
公开(公告)日：2003-02-18
申请号：US09733499
申请日：2000-12-07
IPC分类号： H01L2976
CPC分类号： H01L27/112 , H01L27/105 , H01L27/11253 , H01L27/11293
摘要： The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type. Specifically, some of the transistors of the ROM cells have their polysilicon layers masked and the ROM cells are then implanted by a first dopant species in the active areas of the exposed transistors. Then the masks are removed from the polysilicon layer, and a second dopant species is implanted in said previously covered layer.
摘要翻译： 本发明涉及一种在双栅型CMOS工艺中制造ROM型多电平存储器的方法。 具体地，ROM单元的一些晶体管的多晶硅层被掩蔽，然后通过暴露的晶体管的有源区域中的第一掺杂物种类注入ROM单元。 然后从多晶硅层去除掩模，并且将第二掺杂物种植在所述预先覆盖的层中。
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22.发明授权Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions 有权具有HV晶体管的电子器件的制造方法和具有水银结的LV晶体管公开(公告)号：US06420769B2
公开(公告)日：2002-07-16
申请号：US09861404
申请日：2001-05-18
IPC分类号： H01L2900
CPC分类号： H01L21/823418 , H01L21/823443 , H01L21/823462 , H01L27/088 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.
摘要翻译： 一种具有以下步骤的制造方法：沉积多晶硅的上层; 限定上层，获得低压晶体管和未定义部分的LV栅极区域; 在LV栅极区域侧向形成LV源极和漏极区域; 在LV源极和漏极区域，LV栅极区域和未限定部分上形成硅化物层; 定义高压晶体管的汞化HV栅极区域; 以及形成不直接由硅化物部分覆盖的HV源极和漏极区域。
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23.发明授权Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions 有权用于制造包括非易失性存储单元和具有浸水结的LV晶体管的电子器件的方法公开(公告)号：US06396101B2
公开(公告)日：2002-05-28
申请号：US09836590
申请日：2001-04-16
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.
摘要翻译： 一种用于制造具有水银结的电子器件（诸如存储器单元和LV晶体管）的方法，其包括：沉积多层硅的上层; 限定上层，获得第一区域上的浮栅区域，在衬底的第二区域上的LV栅极区域和衬底的第一和第三区域上的未定义区域; 在浮动栅极区域侧向形成第一单元源区域; 在LV栅极区域侧向形成LV源极和漏极区域; 在LV源极和漏极区域，LV栅极区域和未限定部分上形成硅化物层; 在所述第三区域上限定HV栅极区域，以及在所述第一区域上选择栅极区域; 在选择栅极区域横向形成源极区域，以及横向于HV栅极区域的源极和漏极区域。
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24.发明授权Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions 有权用于制造具有浮动栅极区域的尺寸控制的非易失性存储单元的工艺公开(公告)号：US06340828B1
公开(公告)日：2002-01-22
申请号：US09587377
申请日：2000-06-01
IPC分类号： H01L29778
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11546 , H01L29/42324
摘要： A manufacturing process including forming a first insulating region on top of an active area; forming a tunnel region laterally to the first insulating region; forming a floating gate region; sealing the floating gate region with an insulating region; forming a control gate region on top of the floating gate region; and forming conductive regions in the active area. The floating gate region is obtained by depositing and defining a semiconductor material layer through a floating gate mask. The floating gate mask has an opening with an internally delimiting side extending at a preset distance from a corresponding externally delimiting side of the mask, and the semiconductor material layer is removed laterally at the external and internal delimiting sides so that the tunnel area's length is defined, by the floating gate mask alone.
摘要翻译： 一种制造方法，包括在有源区域的顶部形成第一绝缘区域; 在所述第一绝缘区域上横向形成隧道区域; 形成浮栅区域; 用绝缘区域密封浮动栅极区域; 在浮置栅极区域的顶部形成控制栅极区域; 以及在有源区域中形成导电区域。 通过通过浮栅掩模沉积和限定半导体材料层来获得浮栅区域。 浮栅掩模具有开口，其内部限定侧以距掩模的对应的外部限定侧延伸预定距离，并且半导体材料层在外部和内部限定侧横向移除，使得隧道区域的长度被限定 ，由浮动门口罩单独使用。
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25.发明授权Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions 有权用于制造包括非易失性存储单元和具有浸水结的LV晶体管的电子器件的方法公开(公告)号：US06281077B1
公开(公告)日：2001-08-28
申请号：US09392937
申请日：1999-09-09
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.
摘要翻译： 一种用于制造具有水银结的电子器件（诸如存储器单元和LV晶体管）的方法，其包括：沉积多层硅的上层; 限定上层，获得第一区域上的浮栅区域，在衬底的第二区域上的LV栅极区域和衬底的第一和第三区域上的未定义区域; 在浮动栅极区域侧向形成第一单元源区域; 在LV栅极区域侧向形成LV源极和漏极区域; 在LV源极和漏极区域，LV栅极区域和未限定部分上形成硅化物层; 在所述第三区域上限定HV栅极区域，以及在所述第一区域上选择栅极区域; 在选择栅极区域横向形成源极区域，以及横向于HV栅极区域的源极和漏极区域。
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26.发明授权Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors 有权用于制造具有非盐化非易失性存储单元，非水银高压晶体管和水银结LV晶体管的电子器件的方法公开(公告)号：US06573130B1
公开(公告)日：2003-06-03
申请号：US09426094
申请日：1999-10-22
IPC分类号： H01L218238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11546
摘要： A process that provides for the manufacture of LV transistors with salicidated junctions on first areas of a substrate, HV transistors on second areas, and memory cells on third areas. The process includes forming LV oxide regions and LV gate regions on the first areas, HV oxide regions on the second areas, selection oxide regions, tunnel oxide regions, and matrix oxide regions on the third areas; forming floating gate regions and insulating regions on the tunnel oxide regions and the matrix oxide regions; forming first LV source and drain regions laterally to the LV gate regions; forming silicide regions on the first source and drain regions and on the LV gate regions; forming semiconductor material regions completely covering the second and third areas; and at the same time forming HV gate regions on the HV oxide regions, forming selection gate regions on the selection oxide regions, and forming control gate regions on the insulating regions through shaping of the semiconductor material regions.
摘要翻译： 提供在衬底的第一区域上制造具有盐渍结的LV晶体管，第二区域上的HV晶体管和第三区域上的存储器单元的方法。 该工艺包括在第一区域上形成LV氧化物区域和LV栅极区域，在第三区域上形成第二区域上的HV氧化物区域，选择氧化物区域，隧道氧化物区域和基质氧化物区域; 在隧道氧化物区域和基体氧化物区域上形成浮栅区域和绝缘区域; 在LV栅极区域上横向形成第一LV源极和漏极区域; 在第一源极和漏极区域以及LV栅极区域上形成硅化物区域; 完全覆盖第二和第三区域的半导体材料区域; 同时在HV氧化物区域上形成HV栅极区域，在选择氧化物区域上形成选择栅极区域，并且通过半导体材料区域的成形在绝缘区域上形成控制栅极区域。
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27.发明授权Simplified DSCP process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells 有权用于制造FLOTOX EEPROM非自动对准半导体存储器单元的简化DSCP过程公开(公告)号：US06479347B1
公开(公告)日：2002-11-12
申请号：US09419617
申请日：1999-10-14
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/11524
摘要： A simplified DSCP process makes non-self-aligned floating gate semiconductor memory cells of the FLOTOX EEPROM type as incorporated to a cell matrix having control circuitry associated therewith, wherein each cell has a selection transistor associated therewith. The process includes at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell; tunnel masking to define the tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing the tunnel oxide; depositing and doping the first polysilicon layer poly1. The process further comprises the following steps: poly1 masking to fully define the floating gate of the cell, the poly1 being removed from the area of the selection transistor during this step; depositing or growing the interpoly dielectric and forming tunnel oxide and interpoly dielectric; depositing or growing the interpoly dielectric and forming the overall gate dielectric of the selection transistor, which will therefore consist of the stacked interpoly dielectric and gate dielectric as previously grown or deposited; matrix masking to only remove interpoly dielectric from the circuitry; depositing and doping a second polysilicon layer poly2; masking the second layer of polysilicon to define the control and selection gate; poly etching in the matrix as far down as the intermediate dielectric layer; poly etching in the circuitry the whole short-circuited poly1/poly2 stack.
摘要翻译： 简化的DSCP处理使得FLOTOX EEPROM类型的非自对准浮置半导体存储器单元并入具有与其相关联的控制电路的单元矩阵，其中每个单元具有与其相关联的选择晶体管。 该方法至少包括以下步骤：生长或沉积选择晶体管和电池的栅介电层; 隧道掩蔽以通过用于清洁半导体表面的专用蚀刻步骤限定隧道区域; 生长隧道氧化物; 沉积和掺杂第一多晶硅层poly1。 该方法还包括以下步骤：poly1掩蔽以完全限定电池的浮置栅极，在该步骤期间，poly1从选择晶体管的区域中去除; 沉积或生长多层电介质并形成隧道氧化物和互聚电介质; 沉积或生长多晶硅电介质并形成选择晶体管的总体栅极电介质，因此其将由先前生长或沉积的堆叠的多晶硅间介质和栅极电介质构成; 矩阵掩蔽只能从电路中去除多晶硅电介质; 沉积和掺杂第二多晶硅层poly2; 掩蔽第二层多晶硅以限定控制和选择门; 在与中间介电层一样远的矩阵中进行多层蚀刻; 整个电路中多晶硅刻蚀了整个短路的poly1 / poly2叠层。
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28.发明授权Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells 有权用于在非对准非易失性半导体存储器单元中定义隧道区域的简化过程公开(公告)号：US06444526B1
公开(公告)日：2002-09-03
申请号：US09419403
申请日：1999-10-14
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A simplified non-DSCP process for the definition of the tunnel area in nonvolatile memory cells with semi-conductor floating gates is presented. The memory cells are non-aligned and are incorporated in a matrix of cells and have associated control circuitry. In additional, to each cell a selection transistor is associated. The process includes at least the following phases: growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells; tunnel mask for defining the area of tunnel; cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semiconductor; and growth of tunnel oxide. Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.
摘要翻译： 提出了一种用于在具有半导体浮动栅极的非易失性存储单元中定义隧道区域的简化非DSCP过程。 存储器单元是非对准的并且被并入到单元矩阵中并且具有相关联的控制电路。 另外，对于每个单元，选择晶体管相关联。 该方法至少包括以下阶段：感测晶体管和电池的栅极的介电层的生长或沉积; 用于定义隧道区域的隧道掩模; 在隧道的区域中清洁栅极介质层的蚀刻直到半导体的表面; 和隧道氧化物的生长。 有利地，隧道掩模在选择晶体管占据的区域的上方延伸。
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公开(公告)号：US06414349B1
公开(公告)日：2002-07-02
申请号：US09517636
申请日：2000-03-03
IPC分类号： H01L2976
CPC分类号： H01L29/42324 , H01L27/115
摘要： To increase the facing surface and thus the coupling between the floating gate and control gate regions of a memory cell, the floating gate and control gate regions have a width that is not constant in different section planes parallel to a longitudinal section plane extending through the source and drain regions of the cell. In particular, the width of the floating gate and control gate regions is smallest in the longitudinal section plane and increases linearly in successive parallel section planes moving away from the longitudinal section plane.
摘要翻译： 为了增加面对表面，从而增加存储单元的浮置栅极和控制栅极区域之间的耦合，浮动栅极和控制栅极区域的宽度在平行于延伸穿过源极的纵向截面平面的不同截面中是不恒定的 和漏极区。 特别地，浮动栅极和控制栅极区域的宽度在纵向截面中最小，并且在远离纵向截面平面的连续平行截面中线性增加。
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30.发明授权Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions 有权用于制造具有浮动栅极区域的尺寸控制的非易失性存储单元的工艺公开(公告)号：US06350652B1
公开(公告)日：2002-02-26
申请号：US09587214
申请日：2000-06-01
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11546 , H01L29/42324
摘要： A manufacturing process including: forming a first insulating region on top of an active area; forming a tunnel region at the side of the first insulating region; depositing and defining a semiconductor material layer using a floating gate mask to form a floating gate region. The floating gate mask has an opening with an internal delimiting side extending at a preset distant from a corresponding outer delimiting side of the mask, so that the floating gate region forms inner a hole, and the tunnel region is defined, as regards its length, by the floating gate ask alone. The hole is filled with a dielectric material layer. The surface of the floating gate region is planarized, and an insulating region of dielectric material is made. A control gate region and conductive regions in the active area are then formed.
摘要翻译： 一种制造方法，包括：在有源区域的顶部形成第一绝缘区域; 在所述第一绝缘区域的侧面形成隧道区域; 使用浮栅掩模沉积和限定半导体材料层以形成浮栅区域。 浮栅掩模具有开口，其内部限定侧在远离掩模的对应的外部界定侧的预设位置延伸，使得浮动栅极区域形成内部孔，并且隧道区域关于其长度被限定， 由浮门单独问道。 该孔填充有介电材料层。 浮置栅极区域的表面被平坦化，并且形成绝缘材料的绝缘区域。 然后形成控制栅极区域和有源区域中的导电区域。
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