公开(公告)号：US07949829B2

公开(公告)日：2011-05-24

申请号：US12566609

申请日：2009-09-24

申请人： Ruchi Wadhawan ,  Jason M. Kassoff ,  George Kong Yiu

发明人： Ruchi Wadhawan ,  Jason M. Kassoff ,  George Kong Yiu

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0802 ,  G06F12/0835 ,  G06F12/12

摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

摘要翻译： 在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。 高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

公开(公告)号：US07698478B2

公开(公告)日：2010-04-13

申请号：US11523330

申请日：2006-09-19

申请人： James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

发明人： James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

IPC分类号： G06F3/00

CPC分类号： H04L47/10 ,  G06F13/28 ,  G06F13/385 ,  H04L47/39

摘要： In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.

摘要翻译： 在一个实施例中，系统包括耦合到处理器的至少一个处理器和外围接口控制器。 进一步耦合以从外围接口接收事务，外围接口控制器被配置为为尚未返回到外围接口上的发射机的多个事务类型的给定事务类型累积释放的信用。 外围接口控制器还被配置为响应于多个释放的信用超过超过分配给给定交易类型的信用总数的阈值量而在外围接口上传输流量控制更新交易。

公开(公告)号：US07426601B2

公开(公告)日：2008-09-16

申请号：US11832841

申请日：2007-08-02

申请人： Sridhar P. Subramanian ,  James B. Keller ,  George Kong Yiu ,  Ruchi Wadhawan

发明人： Sridhar P. Subramanian ,  James B. Keller ,  George Kong Yiu ,  Ruchi Wadhawan

IPC分类号： G06F13/00 ,  G06F13/36

CPC分类号： G06F13/364 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.

摘要翻译： 在各种实施例中，装置包括多个代理和互连。 在一个实施方案中，多种试剂包括第一至第四试剂。 互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还 包括在从第三代理到第四代理的第二通信路径中。 在另一实施例中，每个段由选择电路驱动。 至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。 在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。 仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

公开(公告)号：US20070038791A1

公开(公告)日：2007-02-15

申请号：US11201581

申请日：2005-08-11

申请人： Sridhar Subramanian ,  James Keller ,  Ruchi Wadhawan ,  George Yiu ,  Ramesh Gunna

发明人： Sridhar Subramanian ,  James Keller ,  Ruchi Wadhawan ,  George Yiu ,  Ramesh Gunna

IPC分类号： G06F13/36

CPC分类号： G06F13/362 ,  G06F13/4022

摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

摘要翻译： 在一个实施例中，开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。 在另一个实施例中，预期了一种方法。

公开(公告)号：US08631213B2

公开(公告)日：2014-01-14

申请号：US12883878

申请日：2010-09-16

申请人： Sukalpa Biswas ,  Hao Chen ,  Ruchi Wadhawan

发明人： Sukalpa Biswas ,  Hao Chen ,  Ruchi Wadhawan

IPC分类号： G06F12/00

CPC分类号： G06F13/1694 ,  G06F13/1684

摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

摘要翻译： 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

公开(公告)号：US08566485B2

公开(公告)日：2013-10-22

申请号：US13566485

申请日：2012-08-03

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US20120072678A1

公开(公告)日：2012-03-22

申请号：US12883878

申请日：2010-09-16

申请人： Sukalpa Biswas ,  Hao Chen ,  Ruchi Wadhawan

发明人： Sukalpa Biswas ,  Hao Chen ,  Ruchi Wadhawan

IPC分类号： G06F12/00

CPC分类号： G06F13/1694 ,  G06F13/1684

摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

摘要翻译： 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数在不同端口上接收的调度操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

公开(公告)号：US08032670B2

公开(公告)日：2011-10-04

申请号：US12696589

申请日：2010-01-29

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F3/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US07808999B2

公开(公告)日：2010-10-05

申请号：US12054235

申请日：2008-03-24

申请人： Edmund G. Chen ,  John G. Favor ,  Ruchi Wadhawan ,  Gregory G. Minshall

发明人： Edmund G. Chen ,  John G. Favor ,  Ruchi Wadhawan ,  Gregory G. Minshall

IPC分类号： H04L12/56 ,  H04L12/54 ,  G06F9/44

CPC分类号： H04L49/9094 ,  H04L49/90

摘要： These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets.

摘要翻译： 将参照具体实施方式和附图更好地描述本发明的这些和其它方面。 描述了使用链表对包进行无序处理的方法和装置。 在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。 该方法还包括将关于每个分组的信息存储在共享重排序缓冲器中。 该方法还包括对于多个重排序上下文中的每一个，维护重排序上下文链接列表，其记录其中针对该重排序上下文指定的分组以及当前存储在共享重排序缓冲器中的分组的顺序相对于 全球秩序。 该方法还包括完成处于全局顺序中的至少某些分组的处理，并且至少在某些分组中从全局顺序退出来自共享重排序缓冲器的分组。

公开(公告)号：US07752366B2

公开(公告)日：2010-07-06

申请号：US12263255

申请日：2008-10-31

申请人： Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

发明人： Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

IPC分类号： G06F13/00

CPC分类号： G06F13/362 ,  G06F13/4022

摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

摘要翻译： 在一个实施例中，开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。 在另一个实施例中，预期了一种方法。