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21.发明授权Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data 有权通过线程保存和恢复指向包含有效消息数据的存储器阵列的指针，片上网络中的上下文切换公开(公告)号：US08214845B2
公开(公告)日：2012-07-03
申请号：US12118039
申请日：2008-05-09
CPC分类号： G06F15/7825 , H04L49/109
摘要： A network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.
摘要翻译： 包括IP块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过包括收件箱和发件箱的应用消息传送互连网络适配到网络，IP网络中的一个或多个 块，包括支持多个线程的计算机处理器，NOC还包括分别设置指向当前线程的有效消息数据的收件箱和发送箱的指针的收件箱和发件箱控制器; 以及在当前线程中运行的软件，在上下文切换到新线程时，配置为：保存当前线程的指针值，并重置指针值以识别新线程的有效消息数据，其中收件箱和 发送箱控制器被进一步配置为将当前线程的有效消息数据保留在框中，直到上下文再次切换到当前线程。
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22.发明授权公开(公告)号：US08010750B2
公开(公告)日：2011-08-30
申请号：US12015975
申请日：2008-01-17
IPC分类号： G06F12/00
CPC分类号： G06F12/0833
摘要： A network on chip (‘NOC’) including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），其中所述存储器通信控制器被配置为执行存储器访问指令并且被配置为确定 由存储器访问指令寻址的高速缓存行，高速缓存行的状态是共享，排他或无效之一; 所述存储器通信控制器被配置为如果所述高速缓存行的状态被共享，则向所述NOC的多个IP块广播无效命令; 以及所述存储器通信控制器被配置为仅当所述高速缓存行的状态是排他性时，将无效命令仅发送到控制高速缓存行存储的高速缓存的IP块。
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公开(公告)号：US07958340B2
公开(公告)日：2011-06-07
申请号：US12117875
申请日：2008-05-09
IPC分类号： G06F9/38 , G06F15/173
CPC分类号： G06F11/3404 , G06F15/7825
摘要： Software pipelining on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers. Embodiments of the present invention include implementing a software pipeline on the NOC, including segmenting a computer software application into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID; executing each stage of the software pipeline on a thread of execution on an IP block; monitoring software pipeline performance in real time; and reconfiguring the software pipeline, dynamically, in real time, and in dependence upon the monitored software pipeline performance.
摘要翻译： 芯片上的软件流水线（NOC），NOC包括集成处理器（IP）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和 网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器。 本发明的实施例包括在NOC上实现软件管线，包括将计算机软件应用程序分阶段分段，每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块; 在IP块上执行一个执行线程的软件流水线的每个阶段; 实时监控软件流水线性能; 并且动态地，实时地重新配置软件流水线，并且依赖于监视的软件流水线性能。
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24.发明授权公开(公告)号：US07940265B2
公开(公告)日：2011-05-10
申请号：US11535568
申请日：2006-09-27
CPC分类号： G06T17/005 , G06T1/60 , G06T15/06
摘要： According to embodiments of the invention, separate spatial indexes may be created which correspond to dynamic objects in a three dimensional scene and static objects in the three dimensional scene. By creating separate spatial indexes for static and dynamic objects, only the dynamic spatial index may need to be rebuilt in response to movement or changes in shape of objects in the three dimensional scene. Furthermore, the static and dynamic spatial indexes may be stored in separate portions of an image processing system's memory cache. By storing the static spatial index and the dynamic spatial index in separate portions of the memory cache, the dynamic portion of the memory cache may be updated without affecting the static portion of the spatial index in the memory cache.
摘要翻译： 根据本发明的实施例，可以创建对应于三维场景中的动态对象和三维场景中的静态对象的分开的空间索引。 通过为静态和动态对象创建单独的空间索引，只有动态空间索引可能需要重建，以响应三维场景中对象的移动或变化。 此外，静态和动态空间索引可以存储在图像处理系统的存储器高速缓存的分开的部分中。 通过将静态空间索引和动态空间索引存储在存储器高速缓存的分开的部分中，可以更新存储器高速缓存的动态部分而不影响存储器高速缓存中的空间索引的静态部分。
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25.发明授权公开(公告)号：US07840757B2
公开(公告)日：2010-11-23
申请号：US10901600
申请日：2004-07-29
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.
摘要翻译： 具有直接更新诸如中央处理单元（CPU）或图形处理单元（GPU）的处理器的高速缓存（例如，主要L1高速缓存）存储器的计算机系统。 专用地址保留给高速存储器。 涉及这些保留地址的存储器访问请求直接路由到高速存储器。 不涉及这些保留地址的存储器访问请求被路由到处理器外部的存储器。
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公开(公告)号：US20090201302A1
公开(公告)日：2009-08-13
申请号：US12029647
申请日：2008-02-12
IPC分类号： G06F15/16
CPC分类号： G06T1/20
摘要： Graphics rendering on a network on chip (‘NOC’) including receiving, in the geometry processor, a representation of an object to be rendered; converting, by the geometry processor, the representation of the object to two dimensional primitives; sending, by the geometry processor, the primitives to the plurality of scan converters; converting, by the scan converters, the primitives to fragments, each fragment comprising one or more portions of a pixel; for each fragment: selecting, by the scan converter for the fragment in dependence upon sorting rules, a pixel processor to process the fragment; sending, by the scan converter to the pixel processor, the fragment; and processing, by the pixel processor, the fragment to produce pixels for an image.
摘要翻译： 包括在芯片上的图形渲染（“NOC”），包括在几何处理器中接收要呈现的对象的表示; 通过几何处理器将对象的表示转换成二维原语; 由所述几何处理器将所述原语发送到所述多个扫描转换器; 由扫描转换器将原语转换成片段，每个片段包括像素的一个或多个部分; 对于每个片段：由扫描转换器根据排序规则选择片段以处理片段的像素处理器; 由扫描转换器向像素处理器发送片段; 以及由所述像素处理器处理所述片段以产生用于图像的像素。
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公开(公告)号：US20090125706A1
公开(公告)日：2009-05-14
申请号：US11936873
申请日：2007-11-08
IPC分类号： G06F9/38
CPC分类号： G06F9/5038 , G06F9/30047 , G06F9/3851 , G06F9/3885 , G06F15/7825 , G06F15/8053 , G06F2209/5017
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器， 其中每个存储器通信控制器控制IP块和存储器之间的通信以及控制通过路由器进行IP间块通信的每个网络接口控制器，NOC还包括被分段成阶段的计算机软件应用，每个级包括计算机程序的可灵活配置的模块 由阶段ID标识的指令，每个阶段在IP块上的执行线程上执行。
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公开(公告)号：US08438578B2
公开(公告)日：2013-05-07
申请号：US12135364
申请日：2008-06-09
CPC分类号： G06F9/546 , G06F15/7825 , H04L45/00
摘要： Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.
摘要翻译： 芯片上的数据处理（“NOC”）包括IP块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应于网络; 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段在IP块上的执行线程上执行; 并且所述IP块中的至少一个包括对至少一个IP块执行至少一些数据通信业务的输入/输出（“I / O”）加速器。
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公开(公告)号：US20120203971A1
公开(公告)日：2012-08-09
申请号：US13445005
申请日：2012-04-12
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/126 , G06F15/7825
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, a multiplicity of computer processors, each computer processor implementing a plurality of hardware threads of execution; and computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器， 计算机处理器的多样性，每个计算机处理器实现多个硬件执行线程; 和计算机存储器，计算机存储器以页面组织并且可操作地耦合到一个或多个计算机处理器，该计算机存储器包括集合关联高速缓存，该高速缓存包括以集合组织的高速缓存方式，高速缓存在执行的硬件线程之间共享 计算机存储器的每一页被限制用于通过一类替换向量的一个替换向量到高速缓存的特定方式进行高速缓存，存储器的每一页被进一步限制用于通过替换向量分类的一个或多个位进行高速缓存到特定的一组方式 缓存。
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30.发明授权公开(公告)号：US07917703B2
公开(公告)日：2011-03-29
申请号：US11955553
申请日：2007-12-13
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0837 , G06F15/7825
摘要： A network on chip (‘NOC’) comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block coupled to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器耦合到路由器，NOC 还包括在通过其接收到无效命令的网络的路由器上的端口，包括高速缓存行的标识的无效命令，表示使高速缓存行无效的指令的无效命令，被配置为将无效命令发送到 由路由器服务的IP块; 路由器还配置为如果端口是垂直端口，则将无效命令水平和垂直地发送到相邻路由器; 并且该路由器还被配置为仅当该端口是水平端口时才将水平地发送到相邻路由器的invalidate命令。
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