公开(公告)号：US10580876B2

公开(公告)日：2020-03-03

申请号：US15914611

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-hyeok Ahn ,  Eun-jung Kim ,  Hui-jung Kim ,  Ki-seok Lee ,  Bong-soo Kim ,  Myeong-dong Lee ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L29/423 ,  H01L21/74 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

公开(公告)号：US10515798B2

公开(公告)日：2019-12-24

申请号：US16120775

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Bong-soo Kim ,  Jin-bum Kim ,  Yoo-sang Hwang

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778 ,  H01L29/24 ,  H01L29/16 ,  H01L29/20

Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming a transition metal oxide pattern on a substrate and forming a transition metal dichalcogenide layer on a top surface and a side surface of a residual portion of the transition metal oxide pattern. The forming the transition metal dichalcogenide layer may include replacing a surface portion of the transition metal oxide pattern with the transition metal dichalcogenide layer. The transition metal dichalcogenide layer includes at least one atomic layer that is substantially parallel to a surface of the residual portion of the transition metal oxide pattern.

公开(公告)号：US20190164976A1

公开(公告)日：2019-05-30

申请号：US16004937

申请日：2018-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-jung Kim ,  Bong-soo Kim ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/768

Abstract: A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.

公开(公告)号：US20130026564A1

公开(公告)日：2013-01-31

申请号：US13644166

申请日：2012-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan-sik Cho ,  Kwang-youl Chun ,  Jae-man Yoon ,  Bong-soo Kim

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L21/768

Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.

Abstract translation: 公开了一种使用凹槽通道阵列制造半导体器件的方法。 提供了具有第一区域和第二区域的衬底，该第一区域和第二区域包括第一区域中的第一晶体管，该第一区域包括部分地填充沟槽的第一栅电极，以及形成在沟槽两侧的源区和漏区， 第一绝缘层。 在基板上形成第一导电层。 通过图案化第一导电层和第一绝缘层来形成漏极区域露出的接触孔。 形成一个填充接触孔的接触塞。 形成通过接触插塞电连接到漏极区的位线，同时通过对第一导电层进行构图而在第二区域中形成第二栅电极。