公开(公告)号：US08929693B2

公开(公告)日：2015-01-06

申请号：US13787918

申请日：2013-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-jae Shin ,  Hyun-il Byun ,  Kwang-hyun Lee ,  Kwan-sik Cho ,  Ho-chul Ji ,  Jung-hyung Pyo ,  Kyoung-ho Ha

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/43

CPC classification number: G02B6/12 ,  G02B6/4207 ,  G02B6/4214 ,  G02B6/428 ,  G02B6/43 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: A semiconductor package and a semiconductor device including the same. The semiconductor package includes: a package substrate; a plurality of connection elements that are disposed on the package substrate; and a semiconductor chip that includes at least one optical input/output element that transmits/receives an optical signal to/from the outside at an optical input/output angle with respect to a direction perpendicular to a bottom surface of the package substrate, and is electrically connected to the package substrate through the plurality of connection.

Abstract translation: 一种半导体封装和包括该半导体封装的半导体器件。 半导体封装包括：封装衬底; 多个连接元件，其设置在所述封装基板上; 以及半导体芯片，其包括至少一个光输入/输出元件，所述至少一个光输入/输出元件相对于垂直于所述封装基板的底面的方向以光输入/输出角度向/从外部发送/接收光信号，并且是 通过多个连接电连接到封装衬底。

公开(公告)号：US08557664B2

公开(公告)日：2013-10-15

申请号：US13644166

申请日：2012-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan-sik Cho ,  Kwang-youl Chun ,  Jae-man Yoon ,  Bong-soo Kim

IPC: H01L21/336

CPC classification number: H01L21/768

Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.

Abstract translation: 公开了一种使用凹槽通道阵列制造半导体器件的方法。 提供了具有第一区域和第二区域的衬底，该第一区域和第二区域包括第一区域中的第一晶体管，该第一区域包括部分地填充沟槽的第一栅电极，以及形成在沟槽两侧的源区和漏区， 第一绝缘层。 在基板上形成第一导电层。 通过图案化第一导电层和第一绝缘层来形成漏极区域露出的接触孔。 形成一个填充接触孔的接触塞。 形成通过接触插塞电连接到漏极区的位线，同时通过对第一导电层进行构图而在第二区域中形成第二栅电极。

公开(公告)号：US20130330035A1

公开(公告)日：2013-12-12

申请号：US13787918

申请日：2013-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Jae Shin ,  Hyun-il Byun ,  Kwang-hyun Lee ,  Kwan-sik Cho ,  Ho-chul Ji ,  Jung-hyung Pyo ,  Kyoung-ho Ha

IPC: G02B6/12

CPC classification number: G02B6/12 ,  G02B6/4207 ,  G02B6/4214 ,  G02B6/428 ,  G02B6/43 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: A semiconductor package and a semiconductor device including the same. The semiconductor package includes: a package substrate; a plurality of connection elements that are disposed on the package substrate; and a semiconductor chip that includes at least one optical input/output element that transmits/receives an optical signal to/from the outside at an optical input/output angle with respect to a direction perpendicular to a bottom surface of the package substrate, and is electrically connected to the package substrate through the plurality of connection

Abstract translation: 一种半导体封装和包括该半导体封装的半导体器件。 半导体封装包括：封装衬底; 多个连接元件，其设置在所述封装基板上; 以及半导体芯片，其包括至少一个光输入/输出元件，所述至少一个光输入/输出元件相对于垂直于所述封装基板的底面的方向以光输入/输出角度向/从外部发送/接收光信号，并且是 通过多个连接电连接到封装衬底

公开(公告)号：US20130026564A1

公开(公告)日：2013-01-31

申请号：US13644166

申请日：2012-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan-sik Cho ,  Kwang-youl Chun ,  Jae-man Yoon ,  Bong-soo Kim

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L21/768

Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.

Abstract translation: 公开了一种使用凹槽通道阵列制造半导体器件的方法。 提供了具有第一区域和第二区域的衬底，该第一区域和第二区域包括第一区域中的第一晶体管，该第一区域包括部分地填充沟槽的第一栅电极，以及形成在沟槽两侧的源区和漏区， 第一绝缘层。 在基板上形成第一导电层。 通过图案化第一导电层和第一绝缘层来形成漏极区域露出的接触孔。 形成一个填充接触孔的接触塞。 形成通过接触插塞电连接到漏极区的位线，同时通过对第一导电层进行构图而在第二区域中形成第二栅电极。