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    ORGANIC LIGHT-EMITTING DEVICE
    25.
    发明申请
    ORGANIC LIGHT-EMITTING DEVICE 审中-公开

    公开(公告)号：US20190157603A1

    公开(公告)日：2019-05-23

    申请号：US16161574

    申请日：2018-10-16

    Applicant: Samsung Electronics Co., Ltd. ,  Samsung SDI Co., Ltd.

    Inventor： Jongsoo KIM ,  Joonghyuk KIM ,  Namheon LEE ,  Inkoo KIM ,  Daun JEONG ,  Sunghan KIM ,  Myungsun SIM ,  Sooghang IHN

    IPC: H01L51/52 ,  H01L51/50 ,  H01L51/00

    Abstract: An organic light-emitting device including a first electrode, a second electrode facing the first electrode, and an emission layer disposed between the first electrode and the second electrode, wherein the emission layer includes a first material not including an electron transport moiety, a second material including at least one electron transport moiety, a third material having reorganization energy of about 0.4 eV or more, and a light-emitting material, wherein the first material, the second material, the third material, and the light-emitting material are different from one another, and wherein a ratio of a light-emitting component emitted from the light-emitting material to a total of light-emitting components emitted from the emission layer is about 90% or more.

    SEMICONDUCTOR DEVICE AND A DATA STORAGE SYSTEM INCLUDING THE SAME
    30.
    发明申请
    SEMICONDUCTOR DEVICE AND A DATA STORAGE SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220254807A1

    公开(公告)日：2022-08-11

    申请号：US17507929

    申请日：2021-10-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongsoo KIM ,  Sunil Shim ,  Juyoung Lim ,  Wonseok Cho

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

    Abstract: A semiconductor device including: a memory cell array region and a staircase region on a pattern structure; a stack structure including insulating layers and gate layers with gate pads alternately stacked in a vertical direction; a separation structure penetrating through the stack structure and contacting the pattern structure; a memory vertical structure penetrating through the stack structure and contacting the pattern structure; a support vertical structure penetrating through the stack structure and contacting the pattern structure; gate contact plugs disposed on the gate pads; and a peripheral contact plug spaced apart from the gate layers, wherein an upper surface of the memory vertical structure is at a first level, an upper surface of the peripheral contact plug is at a second level, an upper surface of the separation structure is at a third level, and upper surfaces of the gate contact plugs are at a fourth level.

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