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    Integrated circuit and electronic device for controlling function modules in low-power state according to operation state, and control method therefor
    1.
    发明授权
    Integrated circuit and electronic device for controlling function modules in low-power state according to operation state, and control method therefor 有权

    公开(公告)号：US11307608B2

    公开(公告)日：2022-04-19

    申请号：US16971049

    申请日：2019-03-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Minwoo Song ,  Younghyun Ban ,  Juyoung Lim ,  Chulmin Lee

    IPC分类号： G06F1/10 ,  G06F1/06 ,  H03K5/00

    摘要： Disclosed are an integrated circuit for controlling function modules to a low-power status depending on an operating status, an electronic device, and a control method thereof. An integrated circuit includes at least one clock generator, a clock distribution circuit that distributes a clock generated by the at least one clock generator, a plurality of function modules that receive the clock distributed by the clock distribution circuit, a monitoring circuit that monitors operating statuses of the at least one clock generator and the clock distribution circuit, a memory, and at least one control circuit. When the operating statuses of the at least one clock generator and the clock distribution circuit monitored by the monitoring circuit correspond to a specified operating status, the at least one control circuit is configured to control at least one of at least one function module of the plurality of function modules, the at least one clock generator, or the clock distribution circuit based on a specified control method. Moreover, various embodiment found through the disclosure are possible.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220189988A1

    公开(公告)日：2022-06-16

    申请号：US17384329

    申请日：2021-07-23

    申请人： Samsung Electronics Co., Ltd.

    发明人： HangKyu Kang ,  Jongsoo Kim ,  Juyoung Lim ,  Wonseok Cho

    IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/11519 ,  H01L23/528

    摘要： A semiconductor device includes a substrate having a first region, a second region, and a third region with gate electrodes spaced apart from each other in the first region and the second region. The semiconductor device also includes interlayer insulating layers alternately stacked with the gate electrodes, channel structures passing through the gate electrodes in the first region, first dummy structures passing through the gate electrodes in the second region, the first dummy structures disposed adjacent to the first region, second dummy structures passing through the gate electrodes in the second region, the second dummy structures disposed adjacent to the third region, and having different shapes from the first dummy structures, and support structures passing through the gate electrodes in the third region. A size of each of the second dummy structures is larger than a size of each of the support structures.

    SEMICONDUCTOR DEVICE AND A DATA STORAGE SYSTEM INCLUDING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND A DATA STORAGE SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220254807A1

    公开(公告)日：2022-08-11

    申请号：US17507929

    申请日：2021-10-22

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jongsoo KIM ,  Sunil Shim ,  Juyoung Lim ,  Wonseok Cho

    IPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

    摘要： A semiconductor device including: a memory cell array region and a staircase region on a pattern structure; a stack structure including insulating layers and gate layers with gate pads alternately stacked in a vertical direction; a separation structure penetrating through the stack structure and contacting the pattern structure; a memory vertical structure penetrating through the stack structure and contacting the pattern structure; a support vertical structure penetrating through the stack structure and contacting the pattern structure; gate contact plugs disposed on the gate pads; and a peripheral contact plug spaced apart from the gate layers, wherein an upper surface of the memory vertical structure is at a first level, an upper surface of the peripheral contact plug is at a second level, an upper surface of the separation structure is at a third level, and upper surfaces of the gate contact plugs are at a fourth level.