-
1.发明授权Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors 有权具有横向集成的地选择晶体管的垂直集成的非易失性存储器件公开(公告)号：US09202571B2
公开(公告)日：2015-12-01
申请号：US14272765
申请日：2014-05-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunil Shim , Jaehun Jeong , Jaehoon Jang , Kihyun Kim
IPC: G11C11/34 , G11C16/04 , H01L27/115
CPC classification number: H01L27/11582 , G11C16/0408 , G11C16/0466 , G11C16/0483 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/1157
Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.
Abstract translation: 非易失性存储器件利用垂直堆叠的非易失性存储器单元串（例如，NAND型串），其可选择性地耦合到衬底内的公共源极线。 该选择耦合可以由具有不同阈值电压的横向接地选择晶体管提供，这些阈值电压考虑了非垂直堆叠的非易失性存储单元串与公共源极线之间的不同横向间隔。
-
公开(公告)号：US08946665B2
公开(公告)日：2015-02-03
申请号：US13938833
申请日：2013-07-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunil Shim , Wonseok Cho , Woonkyung Lee
IPC: H01L29/78 , H01L21/28 , H01L29/792 , H01L21/8239 , H01L27/11 , H01L27/115 , H01L23/538 , H01L27/24 , H01L45/00
CPC classification number: H01L27/11582 , H01L23/5384 , H01L27/11556 , H01L27/11565 , H01L27/2409 , H01L27/2481 , H01L27/249 , H01L29/7827 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.
Abstract translation: 半导体器件包括多个第一绝缘层和多个第二层，其交替地和垂直地堆叠在基板上。 多个第二层中的每一个包括由第二绝缘层水平隔开的水平电极。 接触插塞穿透多个第二绝缘层和多个第二层中的第二绝缘层。
-
3.发明申请NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME 有权具有垂直结构的非易失性存储器件及其操作方法公开(公告)号：US20130201758A1
公开(公告)日：2013-08-08
申请号：US13836212
申请日：2013-03-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Doogon Kim , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jaehun Jeong
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C16/0483 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L29/66825 , H01L29/7881
Abstract: Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.
Abstract translation: 提供了一种操作非易失性存储器件的方法。 该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到 与第一和第二NAND串的存储单元相连的字线。
-
公开(公告)号：US20240422975A1
公开(公告)日：2024-12-19
申请号：US18590354
申请日：2024-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwangyoung Jung , Sunil Shim , Seung-Jun Lee , Joohyun Lim , Yoojin Jeon
Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure on a peripheral substrate, a cell array structure on the peripheral circuit structure, the cell array structure including a cell array region and an outer region, a source structure on the cell array region, a base pattern on the outer region, a cell vertical structure that extends into the cell array structure in the cell array region and is electrically connected to the source structure, an outer vertical structure that extends into the cell array structure in the outer region, and a filling pattern that extends from the outer vertical structure and into the base pattern. The filling pattern defines a void, a top end of the cell vertical structure extends from the peripheral substrate by a first distance, and a top surface of the source structure extends from the peripheral substrate by a second distance.
-
公开(公告)号：US10903227B2
公开(公告)日：2021-01-26
申请号：US15609578
申请日：2017-05-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunil Shim , Wonseok Cho , Woonkyung Lee
IPC: H01L27/11582 , H01L29/78 , H01L23/538 , H01L27/24 , H01L27/11565 , H01L27/11556 , H01L45/00
Abstract: A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.
-
Patent Agency Ranking
公开(公告)号：USRE46623E1
公开(公告)日：2017-12-05
申请号：US14737811
申请日：2015-06-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunil Shim , Sunghoi Hur , Kihyun Kim , Hansoo Kim , Jaehun Jeong
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
Abstract: In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.
-
7.发明授权公开(公告)号：US08767473B2
公开(公告)日：2014-07-01
申请号：US13962451
申请日：2013-08-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunil Shim , Sunghoi Hur , Kihyun Kim , Hansoo Kim , Jaehun Jeong
IPC: G11C16/00
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
Abstract: In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.
Abstract translation: 在具有相对于衬底在水平和垂直方向上延伸的存储器单元阵列的三维存储器件的多位编程的方法中，该方法包括首先将要编程的存储器单元编程为第一组 状态。 然后，首先对与第一组状态中的一个相邻的要存储单元相邻的至少一个相邻存储单元进行编程。 在对所述至少一个相邻存储器单元进行第一编程之后，将要编程的存储器单元的第二编程为第二组状态之一，其中所述第二组状态具有大于所述状态数 第一套状态。
-
公开(公告)号：US12125535B2
公开(公告)日：2024-10-22
申请号：US17698627
申请日：2022-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwanyong Kim , Sunil Shim , Wonseok Cho
CPC classification number: G11C16/08 , G11C16/0466 , G11C16/0483
Abstract: An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.
-
公开(公告)号：US11770929B2
公开(公告)日：2023-09-26
申请号：US16993345
申请日：2020-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunil Shim , Suhyeong Lee , Taisoo Lim
CPC classification number: H10B43/27 , H01L29/40114 , H01L29/40117 , H01L29/4234 , H01L29/42324 , H10B41/27 , H10B41/35 , H10B43/35
Abstract: A semiconductor device includes gate layers stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and channel structures penetrating the gate layers and extending in the first direction, each of the channel structures includes first dielectric layers on side surfaces of the gate layers, respectively, and spaced apart from each other in the first direction, electric charge storage layers on side surfaces of the first dielectric layers, respectively, and spaced apart from each other in the first direction, a second dielectric layer extending perpendicularly to the substrate to conform to side surfaces of the electric change storage layers, and a channel layer extending perpendicularly, and each of the first dielectric layers has a first maximum length, and each of the electric charge storage layers has a second maximum length greater than the first maximum length in the first direction.
-
公开(公告)号：US11637117B2
公开(公告)日：2023-04-25
申请号：US17032277
申请日：2020-09-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyojoon Ryu , Kwanyong Kim , Seogoo Kang , Sunil Shim , Wonseok Cho , Jeehon Han
IPC: H01L27/1157 , H01L23/522 , H01L27/11573 , H01L27/11582 , H01L27/11565
Abstract: A semiconductor device includes; a memory stack disposed on a substrate and including a lower gate electrode, an upper gate stack including a string selection line, a vertically extending memory gate contact disposed on the lower gate electrode, and a vertically extending selection line stud disposed on the string selection line. The string selection line includes a material different from that of the lower gate electrode, and the selection line stud includes a material different from that of the memory gate contact.
-
-
-
-
-
-
-
-
-
Search Results
35
records
(took 0.025 seconds)
