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公开(公告)号：US10903227B2
公开(公告)日：2021-01-26
申请号：US15609578
申请日：2017-05-31
发明人： Sunil Shim , Wonseok Cho , Woonkyung Lee
IPC分类号： H01L27/11582 , H01L29/78 , H01L23/538 , H01L27/24 , H01L27/11565 , H01L27/11556 , H01L45/00
摘要： A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.
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公开(公告)号：USRE46623E1
公开(公告)日：2017-12-05
申请号：US14737811
申请日：2015-06-12
发明人： Sunil Shim , Sunghoi Hur , Kihyun Kim , Hansoo Kim , Jaehun Jeong
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.
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3.发明授权公开(公告)号：US08767473B2
公开(公告)日：2014-07-01
申请号：US13962451
申请日：2013-08-08
发明人： Sunil Shim , Sunghoi Hur , Kihyun Kim , Hansoo Kim , Jaehun Jeong
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.
摘要翻译： 在具有相对于衬底在水平和垂直方向上延伸的存储器单元阵列的三维存储器件的多位编程的方法中，该方法包括首先将要编程的存储器单元编程为第一组 状态。 然后，首先对与第一组状态中的一个相邻的要存储单元相邻的至少一个相邻存储单元进行编程。 在对所述至少一个相邻存储器单元进行第一编程之后，将要编程的存储器单元的第二编程为第二组状态之一，其中所述第二组状态具有大于所述状态数 第一套状态。
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4.发明授权Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors 有权具有横向集成的地选择晶体管的垂直集成的非易失性存储器件公开(公告)号：US09202571B2
公开(公告)日：2015-12-01
申请号：US14272765
申请日：2014-05-08
发明人： Sunil Shim , Jaehun Jeong , Jaehoon Jang , Kihyun Kim
IPC分类号： G11C11/34 , G11C16/04 , H01L27/115
CPC分类号： H01L27/11582 , G11C16/0408 , G11C16/0466 , G11C16/0483 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/1157
摘要： Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.
摘要翻译： 非易失性存储器件利用垂直堆叠的非易失性存储器单元串（例如，NAND型串），其可选择性地耦合到衬底内的公共源极线。 该选择耦合可以由具有不同阈值电压的横向接地选择晶体管提供，这些阈值电压考虑了非垂直堆叠的非易失性存储单元串与公共源极线之间的不同横向间隔。
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公开(公告)号：US08946665B2
公开(公告)日：2015-02-03
申请号：US13938833
申请日：2013-07-10
发明人： Sunil Shim , Wonseok Cho , Woonkyung Lee
IPC分类号： H01L29/78 , H01L21/28 , H01L29/792 , H01L21/8239 , H01L27/11 , H01L27/115 , H01L23/538 , H01L27/24 , H01L45/00
CPC分类号： H01L27/11582 , H01L23/5384 , H01L27/11556 , H01L27/11565 , H01L27/2409 , H01L27/2481 , H01L27/249 , H01L29/7827 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.
摘要翻译： 半导体器件包括多个第一绝缘层和多个第二层，其交替地和垂直地堆叠在基板上。 多个第二层中的每一个包括由第二绝缘层水平隔开的水平电极。 接触插塞穿透多个第二绝缘层和多个第二层中的第二绝缘层。
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6.发明申请NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME 有权具有垂直结构的非易失性存储器件及其操作方法公开(公告)号：US20130201758A1
公开(公告)日：2013-08-08
申请号：US13836212
申请日：2013-03-15
发明人： Doogon Kim , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jaehun Jeong
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L29/66825 , H01L29/7881
摘要： Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.
摘要翻译： 提供了一种操作非易失性存储器件的方法。 该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到 与第一和第二NAND串的存储单元相连的字线。
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7.发明授权公开(公告)号：US12082412B2
公开(公告)日：2024-09-03
申请号：US17154159
申请日：2021-01-21
发明人： Ju-Young Lim , Jongsoo Kim , Jesuk Moon , Dongwoo Kim , Sunil Shim , Wonseok Cho
摘要： A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.
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公开(公告)号：US11653493B2
公开(公告)日：2023-05-16
申请号：US16874159
申请日：2020-05-14
发明人： Sanghoon Jeong , Sangjun Hong , Sunil Shim , Kyunghyun Kim , Changsup Mun
IPC分类号： H01L27/11568 , H01L27/11556 , G11C5/02 , H01L27/11582
CPC分类号： H01L27/11556 , G11C5/025 , H01L27/11582
摘要： A semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers.
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公开(公告)号：US11295815B2
公开(公告)日：2022-04-05
申请号：US16781986
申请日：2020-02-04
发明人： Kwanyong Kim , Sunil Shim , Wonseok Cho
摘要： An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.
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公开(公告)号：US09698155B2
公开(公告)日：2017-07-04
申请号：US14563432
申请日：2014-12-08
发明人： Sunil Shim , Wonseok Cho , Woonkyung Lee
IPC分类号： H01L27/115 , H01L27/24 , H01L27/11582 , H01L29/78 , H01L23/538 , H01L27/11565 , H01L27/11556 , H01L45/00
CPC分类号： H01L27/11582 , H01L23/5384 , H01L27/11556 , H01L27/11565 , H01L27/2409 , H01L27/2481 , H01L27/249 , H01L29/7827 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.
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