Programming methods for three-dimensional memory devices having multi-bit programming, and three-dimensional memory devices programmed thereby
    3.
    发明授权
    Programming methods for three-dimensional memory devices having multi-bit programming, and three-dimensional memory devices programmed thereby 有权
    具有多位编程的三维存储器件的编程方法以及由此编程的三维存储器件

    公开(公告)号:US08767473B2

    公开(公告)日:2014-07-01

    申请号:US13962451

    申请日:2013-08-08

    IPC分类号: G11C16/00

    摘要: In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.

    摘要翻译: 在具有相对于衬底在水平和垂直方向上延伸的存储器单元阵列的三维存储器件的多位编程的方法中,该方法包括首先将要编程的存储器单元编程为第一组 状态。 然后,首先对与第一组状态中的一个相邻的要存储单元相邻的至少一个相邻存储单元进行编程。 在对所述至少一个相邻存储器单元进行第一编程之后,将要编程的存储器单元的第二编程为第二组状态之一,其中所述第二组状态具有大于所述状态数 第一套状态。

    Semiconductor memory device and method of manufacturing the same

    公开(公告)号:US11653493B2

    公开(公告)日:2023-05-16

    申请号:US16874159

    申请日:2020-05-14

    摘要: A semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers.

    Integrated circuit device including vertical memory

    公开(公告)号:US11295815B2

    公开(公告)日:2022-04-05

    申请号:US16781986

    申请日:2020-02-04

    IPC分类号: G11C16/08 G11C16/04

    摘要: An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.