公开(公告)号：US09293599B2

公开(公告)日：2016-03-22

申请号：US14278705

申请日：2014-05-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Suguru Hondo ,  Daigo Ito

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L23/31 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L23/3192 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor with stable electric characteristics is provided. A transistor with small variation in electrical characteristics is provided. A miniaturized transistor is provided. A transistor having low off-state current is provided. A transistor having high on-state current is provided. A semiconductor device including the transistor is provided. One embodiment of the present invention is a semiconductor device including an island-shaped stack including a base insulating film and an oxide semiconductor film over the base insulating film; a protective insulating film facing a side surface of the stack and not facing a top surface of the stack; a first conductive film and a second conductive film which are provided over and in contact with the stack to be apart from each other; an insulating film over the stack, the first conductive film, and the second conductive film; and a third conductive film over the insulating film.

Abstract translation: 提供具有稳定电特性的晶体管。 提供了一种电特性变化小的晶体管。 提供了一种小型化的晶体管。 提供具有低截止电流的晶体管。 提供具有高导通电流的晶体管。 提供包括晶体管的半导体器件。 本发明的一个实施例是一种半导体器件，其包括在基底绝缘膜上的包括基底绝缘膜和氧化物半导体膜的岛状叠层; 面向堆叠的侧表面并且不面向堆叠的顶表面的保护性绝缘膜; 第一导电膜和第二导电膜，其设置在堆叠之间并与堆叠接触以彼此分开; 叠层上的绝缘膜，第一导电膜和第二导电膜; 和绝缘膜上的第三导电膜。

公开(公告)号：US20150214377A1

公开(公告)日：2015-07-30

申请号：US14601625

申请日：2015-01-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Kazuya Hanaoka

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device having favorable electric characteristics is provided. An oxide semiconductor layer includes first and second regions apart from each other, a third region which is between the first and second regions and overlaps with a gate electrode layer with a gate insulating film provided therebetween, a fourth region between the first and third regions, and a fifth region between the second and third regions. A source electrode layer includes first and second conductive layers. A drain electrode layer includes third and fourth conductive layers. The first conductive layer is formed only over the first region. The second conductive layer is in contact with an insulating layer, the first conductive layer, and the first region. The third conductive layer is formed only over the second region. The fourth conductive layer is in contact with the insulating layer, the third conductive layer, and the second region.

Abstract translation: 提供了具有良好的电特性的半导体器件。 氧化物半导体层包括彼此分开的第一和第二区域，位于第一和第二区域之间并与其间设置有栅极绝缘膜的栅电极层重叠的第三区域，第一和第三区域之间的第四区域， 以及第二和第三区域之间的第五区域。 源极电极层包括第一和第二导电层。 漏电极层包括第三和第四导电层。 第一导电层仅形成在第一区域上。 第二导电层与绝缘层，第一导电层和第一区域接触。 第三导电层仅形成在第二区域上。 第四导电层与绝缘层，第三导电层和第二区域接触。

公开(公告)号：US20140209898A1

公开(公告)日：2014-07-31

申请号：US14162364

申请日：2014-01-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiaki Yamamoto ,  Koichi Ito ,  Motomu Kurata ,  Taiga Muraoka ,  Daigo Ito

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: When an oxide semiconductor film is microfabricated to have an island shape, with the use of a hard mask, unevenness of an end portion of the oxide semiconductor film can be suppressed. Specifically, a hard mask is formed over the oxide semiconductor film, a resist is formed over the hard mask, light exposure is performed to form a resist mask, the hard mask is processed using the resist mask as a mask, the oxide semiconductor film is processed using the processed hard mask as a mask, the resist mask and the processed hard mask are removed, a source electrode and a drain electrode are formed in contact with the processed oxide semiconductor film, a gate insulating film is formed over the source electrode and the drain electrode, and a gate electrode is formed over the gate insulating film, the gate electrode overlapping with the oxide semiconductor film.

Abstract translation: 当氧化物半导体膜被微细化以具有岛状时，通过使用硬掩模，可以抑制氧化物半导体膜的端部的不均匀性。 具体地，在氧化物半导体膜上形成硬掩模，在硬掩模上形成抗蚀剂，进行曝光以形成抗蚀剂掩模，使用抗蚀剂掩模作为掩模来处理硬掩模，氧化物半导体膜为 使用处理后的硬掩模作为掩模处理，除去抗蚀剂掩模和加工的硬掩模，形成与处理的氧化物半导体膜接触的源电极和漏电极，在源极上形成栅极绝缘膜， 漏电极和栅电极形成在栅极绝缘膜上方，栅电极与氧化物半导体膜重叠。