公开(公告)号：US11101386B2

公开(公告)日：2021-08-24

申请号：US16634493

申请日：2018-07-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Ryota Hodo ,  Daigo Ito ,  Hiroaki Honda ,  Satoru Okamoto

IPC: H01L29/786 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/105 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/24 ,  H01L29/417

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor over the oxide; a third conductor over the oxide; a first insulator provided between the oxide and the third conductor and covering a side surface of the third conductor; a second insulator over the third conductor and the first insulator; a third insulator positioned over the first conductor and at a side surface of the second insulator; a fourth insulator positioned over the second conductor and at a side surface of the second insulator; a fourth conductor being in contact with a top surface and a side surface of the third insulator and electrically connected to the first conductor; and a fifth conductor being in contact with a top surface and a side surface of the fourth insulator and electrically connected to the second conductor. The first insulator is between the third insulator and the third conductor, and between the fourth insulator and the third conductor.

公开(公告)号：US09768317B2

公开(公告)日：2017-09-19

申请号：US14961016

申请日：2015-12-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Takahisa Ishiyama ,  Kazuya Hanaoka

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/467 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/467 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78696

Abstract: Provided is a semiconductor device which can suppress an increase in oxygen vacancies in an oxide semiconductor layer and a manufacturing method of the semiconductor device. The semiconductor device includes a first oxide semiconductor layer over the first insulating layer; a second oxide semiconductor layer over the first oxide semiconductor layer; a third oxide semiconductor layer over the second oxide semiconductor layer; a source electrode layer and a drain electrode layer each over the third oxide semiconductor layer; a fourth semiconductor layer over the source and drain electrode layers, and the third oxide semiconductor layer; a gate insulating layer over the fourth oxide semiconductor layer; a gate electrode layer over the gate electrode layer and overlapping with the source and drain electrode layers, and the fourth oxide semiconductor layer; and a second insulating layer over the first insulating layer, and the source, gate, and drain electrode layers.

公开(公告)号：US09691905B2

公开(公告)日：2017-06-27

申请号：US15182812

申请日：2016-06-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Daisuke Matsubayashi ,  Masaharu Nagai ,  Yoshiaki Yamamoto ,  Takashi Hamada ,  Yutaka Okazaki ,  Shinya Sasagawa ,  Motomu Kurata ,  Naoto Yamade

IPC: H01L21/00 ,  H01L21/16 ,  H01L29/786 ,  H01L29/66 ,  H01L21/425 ,  H01L21/46 ,  H01L27/12

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US09379192B2

公开(公告)日：2016-06-28

申请号：US14573463

申请日：2014-12-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Kazuya Hanaoka

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a source electrode layer and a drain electrode layer which are electrically connected to an oxide semiconductor layer, a gate insulating film over the oxide semiconductor layer; the source electrode layer, and the drain electrode layer; and a gate electrode layer that overlaps with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer with the gate insulating film positioned therebetween. The source electrode layer and the drain electrode layer each include a first conductive layer and a second conductive layer. The first conductive layer is in contact with a top surface of the oxide semiconductor layer. The second conductive layer is in contact with a side surface of the oxide semiconductor layer. The first conductive layer and the second conductive layer are electrically connected to each other.

Abstract translation: 提供了具有良好的电气特性的半导体器件。 半导体器件包括与氧化物半导体层电连接的源极电极层和漏极电极层，氧化物半导体层上的栅极绝缘膜; 源极电极层和漏极电极层; 以及栅极电极层，其与氧化物半导体层，源极电极层和漏极电极层重叠，栅极绝缘膜位于它们之间。 源极电极层和漏极电极层各自包括第一导电层和第二导电层。 第一导电层与氧化物半导体层的顶表面接触。 第二导电层与氧化物半导体层的侧表面接触。 第一导电层和第二导电层彼此电连接。

公开(公告)号：US20150001532A1

公开(公告)日：2015-01-01

申请号：US14313008

申请日：2014-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yoshiyuki Kobayashi ,  Daisuke Matsubayashi ,  Akihisa Shimomura ,  Daigo Ito

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696

Abstract: To provide a semiconductor device in which a large current can flow. To provide a semiconductor device which can be driven stably at a high driving voltage. The semiconductor device includes a semiconductor layer, a first electrode and a second electrode electrically connected to the semiconductor layer and apart from each other in a region overlapping with the semiconductor layer, a first gate electrode and a second gate electrode with the semiconductor layer therebetween, a first gate insulating layer between the semiconductor layer and the first gate electrode, and a second gate insulating layer between the semiconductor layer and the second gate electrode. The first gate electrode overlaps with part of the first electrode, the semiconductor layer, and part of the second electrode. The second gate electrode overlaps with the semiconductor layer and part of the first electrode, and does not overlap with the second electrode.

Abstract translation: 提供可以流过大电流的半导体器件。 提供可在高驱动电压下稳定驱动的半导体器件。 半导体器件包括半导体层，第一电极和与半导体层电连接并且在与半导体层重叠的区域中彼此分开的第二电极，第一栅电极和第二栅电极，其间具有半导体层， 在所述半导体层和所述第一栅电极之间的第一栅极绝缘层，以及在所述半导体层和所述第二栅电极之间的第二栅极绝缘层。 第一栅电极与第一电极，半导体层和第二电极的一部分重叠。 第二栅电极与半导体层和第一电极的一部分重叠，并且不与第二电极重叠。

公开(公告)号：US11581439B2

公开(公告)日：2023-02-14

申请号：US16693482

申请日：2019-11-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Yoshiyuki Kobayashi ,  Daisuke Matsubayashi ,  Akihisa Shimomura ,  Daigo Ito

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

Abstract: To provide a semiconductor device in which a large current can flow. To provide a semiconductor device which can be driven stably at a high driving voltage. The semiconductor device includes a semiconductor layer, a first electrode and a second electrode electrically connected to the semiconductor layer and apart from each other in a region overlapping with the semiconductor layer, a first gate electrode and a second gate electrode with the semiconductor layer therebetween, a first gate insulating layer between the semiconductor layer and the first gate electrode, and a second gate insulating layer between the semiconductor layer and the second gate electrode. The first gate electrode overlaps with part of the first electrode, the semiconductor layer, and part of the second electrode. The second gate electrode overlaps with the semiconductor layer and part of the first electrode, and does not overlap with the second electrode.

公开(公告)号：US20140246668A1

公开(公告)日：2014-09-04

申请号：US14190370

申请日：2014-02-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akihisa Shimomura ,  Tomoaki Moriwaka ,  Daigo Ito

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/66969

Abstract: A miniaturized transistor having high electrical characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity can be achieved. The semiconductor device includes a base insulating film, an oxide semiconductor film with a bottom surface and side surfaces in the base insulating film and a top surface exposed from the base insulating film, a source electrode and a drain electrode over the base insulating film and the oxide semiconductor film, a gate insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode over the gate insulating film and overlapping the oxide semiconductor film.

Abstract translation: 提供具有高电特性的小型化晶体管，其产率高。 在包括晶体管的半导体器件中，可以实现高性能，高可靠性和高生产率。 半导体器件包括基底绝缘膜，底表面的氧化物半导体膜和基底绝缘膜中的侧表面以及从基底绝缘膜暴露的顶表面，在基底绝缘膜上的源电极和漏电极以及 氧化物半导体膜，氧化物半导体膜上的栅极绝缘膜，源电极和漏电极以及栅极绝缘膜上的与电极半导体膜重叠的栅电极。

公开(公告)号：US10797180B2

公开(公告)日：2020-10-06

申请号：US16703175

申请日：2019-12-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Daigo Ito ,  Takahisa Ishiyama ,  Katsuaki Tochibayashi ,  Kazuya Hanaoka

IPC: H01L29/786 ,  H01L21/67 ,  H01L27/146 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L27/12

Abstract: The semiconductor device includes a first insulating layer; a first oxide insulating layer over the first insulating layer; an oxide semiconductor layer over the first oxide insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a second oxide insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate insulating layer over the second oxide insulating layer; a gate electrode layer over the gate insulating layer; a second insulating layer over the first insulating layer the source electrode layer, the drain electrode layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer, and a third insulating layer over the first insulating layer, the source electrode layer, the drain electrode layer, and the second insulating layer.

公开(公告)号：US10263117B2

公开(公告)日：2019-04-16

申请号：US14601625

申请日：2015-01-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Kazuya Hanaoka

IPC: H01L29/786

Abstract: A semiconductor device having favorable electric characteristics is provided. An oxide semiconductor layer includes first and second regions apart from each other, a third region which is between the first and second regions and overlaps with a gate electrode layer with a gate insulating film provided therebetween, a fourth region between the first and third regions, and a fifth region between the second and third regions. A source electrode layer includes first and second conductive layers. A drain electrode layer includes third and fourth conductive layers. The first conductive layer is formed only over the first region. The second conductive layer is in contact with an insulating layer, the first conductive layer, and the first region. The third conductive layer is formed only over the second region. The fourth conductive layer is in contact with the insulating layer, the third conductive layer, and the second region.

公开(公告)号：US09871145B2

公开(公告)日：2018-01-16

申请号：US15628699

申请日：2017-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Daisuke Matsubayashi ,  Masaharu Nagai ,  Yoshiaki Yamamoto ,  Takashi Hamada ,  Yutaka Okazaki ,  Shinya Sasagawa ,  Motomu Kurata ,  Naoto Yamade

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/425 ,  H01L21/46 ,  H01L27/12

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).