公开(公告)号：US11264286B2

公开(公告)日：2022-03-01

申请号：US16445778

申请日：2019-06-19

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L29/49 ,  H01L29/06 ,  H01L29/417

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20190189802A1

公开(公告)日：2019-06-20

申请号：US16212632

申请日：2018-12-06

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US10283418B2

公开(公告)日：2019-05-07

申请号：US16027889

申请日：2018-07-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L27/092 ,  H01L27/12 ,  H01L29/161

Abstract: A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.

公开(公告)号：US10204982B2

公开(公告)日：2019-02-12

申请号：US14048232

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Qing Liu ,  Nicolas Loubet

IPC: H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8238

Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.

公开(公告)号：US10177255B2

公开(公告)日：2019-01-08

申请号：US15723152

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US10170475B2

公开(公告)日：2019-01-01

申请号：US15448626

申请日：2017-03-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Stephane Allegret-Maret ,  Kangguo Cheng ,  Bruce Doris ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L27/092 ,  H01L27/11 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417

Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.

公开(公告)号：US10134759B2

公开(公告)日：2018-11-20

申请号：US14182601

申请日：2014-02-18

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Loubet ,  James Kuss

IPC: H01L21/8238 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02

Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of fins, forming a first semiconductor material on sides of a first group of the fins, and forming a second semiconductor material on sides of a second group of the fins. The method may further include forming a dielectric layer overlying the plurality of fins to define first and second groups of nanowires within the dielectric layer, with the first group of nanowires including the first semiconductor material and the second group of nanowires including the second semiconductor material.

公开(公告)号：US20180331106A1

公开(公告)日：2018-11-15

申请号：US16035441

申请日：2018-07-13

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US10043805B2

公开(公告)日：2018-08-07

申请号：US15197509

申请日：2016-06-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US09905478B2

公开(公告)日：2018-02-27

申请号：US15469851

申请日：2017-03-27

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.