公开(公告)号：US20210250010A1

公开(公告)日：2021-08-12

申请号：US17241980

申请日：2021-04-27

Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

Inventor： XiangSheng Li ,  Ru Feng Du

IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00 ,  H04R29/00

Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.

公开(公告)号：US20200295723A1

公开(公告)日：2020-09-17

申请号：US16354760

申请日：2019-03-15

Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

Inventor： Ru Feng Du ,  Qi Yu Liu

IPC: H03G1/04 ,  H03K19/017 ,  H03F3/217 ,  H03K19/096 ,  H03K19/20 ,  H03K19/003 ,  H03G3/30

Abstract: In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.

公开(公告)号：US10530309B2

公开(公告)日：2020-01-07

申请号：US16222281

申请日：2018-12-17

Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

Inventor： Ru Feng Du ,  Qi Yu Liu

IPC: H03F1/32 ,  H03F1/30 ,  H03F1/02 ,  H03F3/45 ,  H03F3/183 ,  H03F3/185 ,  H03F3/187 ,  H03F3/21 ,  H03F3/217 ,  H03G3/34 ,  H04R3/00

Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

公开(公告)号：US09306523B2

公开(公告)日：2016-04-05

申请号：US14478531

申请日：2014-09-05

Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

Inventor： Ru Feng Du ,  Qi Yu Liu

IPC: H04R3/00 ,  H03G3/34

CPC classification number: H03F1/3205 ,  H03F1/0205 ,  H03F1/305 ,  H03F3/183 ,  H03F3/185 ,  H03F3/187 ,  H03F3/211 ,  H03F3/2171 ,  H03F3/2173 ,  H03F3/45179 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2203/21106 ,  H03F2203/45151 ,  H03F2203/45156 ,  H03G3/345 ,  H03G3/348 ,  H04R3/002

Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

Abstract translation: D类放大器接收和放大差分模拟信号，然后差分模拟信号被差分地积分。 两个脉冲宽度调制器产生对应于差分集成模拟信号的脉冲信号，两个功率单元产生输出脉冲信号。 功率单元的输出通过电阻反馈网络耦合到积分器的输入端。 模拟输出单元将脉冲信号转换为输出模拟信号。 差分积分电路实现静音/非静音之间的软转换。 静音时，积分器输出是固定的。 在软转换期间，PWM输出从固定的50％占空比缓慢变化到最终值，以确保由于模式更改而导致输出中没有弹出式噪声。

公开(公告)号：US09231535B2

公开(公告)日：2016-01-05

申请号：US14199773

申请日：2014-03-06

Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

Inventor： Ru Feng Du ,  Qi Yu Liu

IPC: H03F3/38 ,  H03F3/217

CPC classification number: H03F3/2171 ,  H03F3/2175

Abstract: A Class-D amplifier includes a pre-amplifier having an input configured to receive an amplifier reference voltage signal which is ramped at start-up at a fast rate. An integrator has a first input configured to receive an input signal from the pre-amplifier and a second input configured to receive an integrator reference voltage signal which is ramped at start-up at a slower rate. A modulator has an input coupled to an output of the integrator. The modulator generates a pulse width modulated output signal. Operation of the Class-D amplifier is controlled at start-up by applying a slow ramped signal as the integrator reference voltage signal and a fast ramped signal as the amplifier reference voltage so that the pulse width modulated output signal exhibits an increasing change in duty cycle in response to an increasing voltage of the integrator reference voltage signal, and no “pop” is introduced at start-up.

Abstract translation: D类放大器包括前置放大器，其具有被配置为接收在启动时以快速速率斜坡的放大器参考电压信号的输入。 积分器具有被配置为从前置放大器接收输入信号的第一输入和被配置为接收以较慢速率在启动时斜坡上升的积分器参考电压信号的第二输入。 调制器具有耦合到积分器的输出的输入。 调制器产生脉宽调制输出信号。 通过将缓慢斜坡信号作为积分器参考电压信号和快速斜坡信号作为放大器参考电压来控制D类放大器的工作，使得脉宽调制输出信号在占空比上呈现增加的变化 响应于积分器参考电压信号的增加的电压，并且在启动时不引入“弹出”。