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公开(公告)号：US20230035218A1
公开(公告)日：2023-02-02
申请号：US17967449
申请日：2022-10-17
Applicant: STMicroelectronics Asia Pacific Pte Ltd.
Inventor： Yannick Guedon
Abstract: A power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample-and-hold (S&H) circuit having an input coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal that have a same frequency, where the first control signal is configured to turn ON and OFF the first switch alternately, the second control signal is configured to turn ON and OFF the second switch alternately, and where the third control signal determines a sampling time of the first S&H circuit and has a first pre-determined delay from a first edge of the first control signal.
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公开(公告)号：US11509513B2
公开(公告)日：2022-11-22
申请号：US17402108
申请日：2021-08-13
Applicant: STMicroelectronics Asia Pacific Pte Ltd.
Inventor： Yannick Guedon
Abstract: A power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample-and-hold (S&H) circuit having an input coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal that have a same frequency, where the first control signal is configured to turn ON and OFF the first switch alternately, the second control signal is configured to turn ON and OFF the second switch alternately, and where the third control signal determines a sampling time of the first S&H circuit and has a first pre-determined delay from a first edge of the first control signal.
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公开(公告)号：US11271393B1
公开(公告)日：2022-03-08
申请号：US17007633
申请日：2020-08-31
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Supriya Raveendra Hegde , Yannick Guedon , Huiqiao He
Abstract: A wireless-power-system includes a bridge-rectifier having first and second inputs coupled to first and second terminals of a coil, and an output coupled to a rectified voltage node. An excitation circuit is coupled to the first input. A protection circuit has a first connection node capacitively coupled to the first terminal. The protection circuit, in Q-factor measurement mode, clamps the first connection node when the first input is coupled to ground, and connects the first connection node to the rectified voltage node when the first input is coupled to a supply voltage. The protection circuit, in wireless power mode, is acting as one leg of the rectifier. A pass gate circuit is coupled between the first connection node and a sense node, and a sensing circuit is coupled to the sense node and measures a Q-factor of the wireless power system when the protection circuit is in Q-factor measurement mode.
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公开(公告)号：US11165286B1
公开(公告)日：2021-11-02
申请号：US16899990
申请日：2020-06-12
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Teerasak Lee , Chee Weng Cheong , Yannick Guedon , Eng Jye Ng
Abstract: A data demodulating circuit includes a sensing circuit sensing a power signal applied to a coil at first and second times, and outputting an analog value representing a difference in voltage of the power signal at the first and second times. An analog-to-digital converter digitizes the analog value output by the analog voltage differential sensing circuit to produce a digital code. A compensation circuit, over a period of time, compares a present value of the digital code to a first value of the digital code during the period, and subtracts a given value from the present value of the digital code if the present value is greater than the first value but add the given value to the present value of the digital code if the present value is less than the first value. An accumulator accumulates output of the compensation circuit, and a filter filters output of the accumulator.
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公开(公告)号：US11128170B1
公开(公告)日：2021-09-21
申请号：US16897429
申请日：2020-06-10
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Yannick Guedon
Abstract: A power transmission system includes at least one wireless power transmission circuit. A first wireless power reception circuit includes a first circuit comparing a reference voltage to a feedback voltage representing an output voltage produced from received power and delivered to an output node, and adjusting a first control terminal of a device supplying a first rectified voltage until the feedback and reference voltages are equal. A second wireless power reception circuit includes a second circuit modifying a control terminal of a device sourcing a second rectified current produced from received power to the output node, based upon comparison of a reference current to a current representative of the second rectified current. Control circuitry adjusts the reference current until a first rectified voltage generated by the first wireless power reception circuit and a second rectified voltage generated by the second wireless power reception circuit are equal.
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Patent Agency Ranking
公开(公告)号：US09389256B2
公开(公告)日：2016-07-12
申请号：US13717780
申请日：2012-12-18
Inventor： Paolo Angelini , Giovanni Carlo Tripoli , Ernesto Lasalandra , Tommaso Ungaretti , Kien Beng Tan , Yannick Guedon , Dianbo Guo , Sze-Kwang Tan
CPC classification number: G01R27/2605 , G06F3/0418 , G06F3/044
Abstract: Capacitance sensing circuits and methods are provided. The capacitance sensing circuit includes a capacitance-to-voltage converter configured to receive a signal from a capacitance to be sensed and to provide an output signal representative of the capacitance, an output chopper configured to convert the output signal of the capacitance-to-voltage converter to a sensed voltage representative of the capacitance to be sensed, an analog accumulator configured to accumulate sensed voltages during an accumulation period of NA sensing cycles and to provide an accumulated analog value, an amplifier configured to amplify the accumulated analog value, and an analog-to-digital converter configured to convert the amplified accumulated analog value to a digital value representative of the capacitance to be sensed. The analog accumulator may include a low pass filter having a frequency response to filter wideband noise.
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公开(公告)号：US20140292375A1
公开(公告)日：2014-10-02
申请号：US13853870
申请日：2013-03-29
Inventor： Paolo Angelini , Yannick Guedon , Ming Zi Zhu
IPC: G11C27/02
CPC classification number: G06F3/044 , G03G7/00 , G06F3/0418 , G06G7/00
Abstract: Accumulators that operate to fully or partially remove noise from a signal, including removing noise inserted into the signal by the accumulator itself. In some embodiments, an accumulator may be operated in a sampling phase and a transfer phase each time the accumulator samples an input signal. In some such embodiments, an op-amp of an accumulation circuit of the accumulator may be auto-zeroed during some or all of the sampling phases of an accumulation period. In some embodiments in which the op-amp is auto-zeroed during some or all of the sampling phases, the accumulation circuit may include a holding capacitor that, during an auto-zeroing process, holds a value output by the op-amp during a prior transfer phase. Including such a holding capacitor in an accumulator may reduce a voltage that the op-amp output rises following the auto-zero process, which may reduce a bandwidth and noise of the accumulation circuit.
Abstract translation: 用于完全或部分地从信号中去除噪声的累加器，包括消除蓄电池本身插入到信号中的噪声。 在一些实施例中，每当累加器对输入信号进行采样时，累加器可以在采样阶段和传送阶段中操作。 在一些这样的实施例中，累加器的累加电路的运算放大器可以在累积周期的某些或全部采样阶段期间自动归零。 在一些实施例中，在某些或所有采样相位期间运算放大器自动归零，其中累积电路可以包括保持电容器，其在自动归零过程期间保持由运算放大器输出的值 先前转移阶段。 在存储器中包括这种保持电容器可以降低运算放大器输出在自动归零过程之后上升的电压，这可以降低积累电路的带宽和噪声。
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公开(公告)号：US20140077823A1
公开(公告)日：2014-03-20
申请号：US13717780
申请日：2012-12-18
Inventor： Paolo Angelini , Giovanni Carlo Tripoli , Ernesto Lasalandra , Tommaso Ungaretti , Kien Beng Tan , Yannick Guedon , Dianbo Guo , Sze-Kwang Tan
IPC: G01R27/26
CPC classification number: G01R27/2605 , G06F3/0418 , G06F3/044
Abstract: Capacitance sensing circuits and methods are provided. The capacitance sensing circuit includes a capacitance-to-voltage converter configured to receive a signal from a capacitance to be sensed and to provide an output signal representative of the capacitance, an output chopper configured to convert the output signal of the capacitance-to-voltage converter to a sensed voltage representative of the capacitance to be sensed, an analog accumulator configured to accumulate sensed voltages during an accumulation period of NA sensing cycles and to provide an accumulated analog value, an amplifier configured to amplify the accumulated analog value, and an analog-to-digital converter configured to convert the amplified accumulated analog value to a digital value representative of the capacitance to be sensed. The analog accumulator may include a low pass filter having a frequency response to filter wideband noise.
Abstract translation: 提供电容感测电路和方法。 电容感测电路包括：电容 - 电压转换器，被配置为从要感测的电容接收信号并提供表示电容的输出信号;输出斩波器，被配置为转换电容 - 电压的输出信号 转换器到感测的电压，代表要感测的电容;模拟累加器，被配置为在NA感测周期的累积周期期间累积感测电压并提供累加的模拟值，被配置为放大所累积的模拟值的放大器和模拟 配置为将放大的累积模拟值转换为表示要感测的电容的数字值。 模拟累加器可以包括具有对滤波器宽带噪声的频率响应的低通滤波器。
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公开(公告)号：US12074663B2
公开(公告)日：2024-08-27
申请号：US17967449
申请日：2022-10-17
Applicant: STMicroelectronics Asia Pacific Pte Ltd.
Inventor： Yannick Guedon
CPC classification number: H04B5/72 , H02J7/04 , H02J50/12 , H02J50/80 , H04B5/79 , H04L25/4904 , H04L27/06
Abstract: A power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample-and-hold (S&H) circuit having an input coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal that have a same frequency, where the first control signal is configured to turn ON and OFF the first switch alternately, the second control signal is configured to turn ON and OFF the second switch alternately, and where the third control signal determines a sampling time of the first S&H circuit and has a first pre-determined delay from a first edge of the first control signal.
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公开(公告)号：US11408923B2
公开(公告)日：2022-08-09
申请号：US17016963
申请日：2020-09-10
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Yannick Guedon , Teerasak Lee , Supriya Raveendra Hegde
Abstract: A receiver circuit includes a rectifier operable in full-, half-synchronous and asynchronous modes. A measurement circuit, with method, provides for real-time power measurement within the rectifier. The measurements are made based on the average output current from the rectifier delivered to the load and measurements sampled over time of the instantaneous voltage at each input/output node of the rectifier. Equivalent resistance in the rectifier is determined from the measurements and power dissipation calculated from the determined equivalent resistance and the average output current. The instantaneous voltages are synchronously captured through high-voltage AC coupling in order to detect the voltage drop across each element of the rectifier. The sensed voltages are amplified in the low voltage domain and converted by a high-speed analog-to-digital converter in order to produce data useful in computing equivalent resistance values. From these values, power dissipation within the rectifier is calculated and real-time equivalent resistance is available.
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