SENSOR DEVICE AND METHOD FOR FLAME PRESENCE DETECTION

    公开(公告)号:US20240302040A1

    公开(公告)日:2024-09-12

    申请号:US18432795

    申请日:2024-02-05

    CPC classification number: F23N1/002 F23N2227/36 F23N2229/14

    Abstract: A sensor device for detecting a flame comprises a carbon dioxide sensor for detecting a CO2 concentration, a fuel sensor for detecting the combustion of a fuel, an electrostatic charge variation sensor for detecting electrostatic charge variations generated by the flame, and a control unit. The control unit is configured to acquire a carbon dioxide signal indicative of the concentration of carbon dioxide, a fuel signal indicative of the fuel combustion, and an electrostatic charge variation signal indicative of a difference between the electrostatic charge variations detected by a first and a second electrode of the electrostatic charge variation sensor, determine a quantized signal based on the electrostatic charge variation signal, determine an aggregate datum based on the carbon dioxide signal, the fuel signal and the electrostatic charge variation signal, and generate, based on the aggregate datum, a flame signal indicative of the presence or absence of the flame.

    Hardware accelerator device, corresponding system and method of operation

    公开(公告)号:US11996158B2

    公开(公告)日:2024-05-28

    申请号:US18349565

    申请日:2023-07-10

    CPC classification number: G11C29/42 G11C29/12015 G11C29/18 G11C29/4401

    Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

    METHOD OF CALIBRATING A CLOCK SIGNAL, AND CORRESPONDING ELECTRONIC DEVICE AND SYSTEM

    公开(公告)号:US20230291538A1

    公开(公告)日:2023-09-14

    申请号:US18174183

    申请日:2023-02-24

    CPC classification number: H04L7/033 H03K5/26

    Abstract: A method includes providing a reference clock signal having a reference period, providing a sampling clock signal having a sampling clock period shorter than the reference period of the reference clock signal, measuring the first subperiod as a first ratio of the first subperiod to the period of the sampling clock signal, measuring the second subperiod as a second ratio of the second subperiod to the period of the sampling clock signal, detecting a starting edge of a clock signal having a clock period greater than the reference period, producing a reconstructed reference signal based on the first ratio, the second ratio, and the detected starting edge, comparing the clock period of the clock signal with a period of the reconstructed reference signal to obtain a differential signal indicating a difference therebetween, and providing the differential signal to user circuitry for calibrating the clock signal.

    DISCHARGE CIRCUIT AND METHOD FOR VOLTAGE TRANSITION MANAGEMENT

    公开(公告)号:US20230288946A1

    公开(公告)日:2023-09-14

    申请号:US17694182

    申请日:2022-03-14

    CPC classification number: G05F1/56

    Abstract: In an embodiment, a method includes: providing a voltage setpoint to a voltage converter; generating an output voltage at a voltage rail with the voltage converter based on the voltage setpoint; when the voltage setpoint is transitioning from a first voltage setpoint to a second voltage setpoint that has a lower magnitude than the first voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, where the output transistor includes a source terminal coupled to a first terminal of a first resistor, and where a current path of the output transistor is coupled to the voltage rail; and turning off the output transistor after the output voltage reaches the target output voltage corresponding to the second voltage setpoint.

    LED ARRAY DRIVER SYSTEM
    7.
    发明申请

    公开(公告)号:US20230135666A1

    公开(公告)日:2023-05-04

    申请号:US18062929

    申请日:2022-12-07

    Abstract: An embodiment LED driver system comprises a power transistor configured to be selectively activated for generating a driving current for an array of LEDs, the power transistor having a first conduction terminal coupled to the array of LEDs and a second conduction terminal coupled to a reference resistor; an operational amplifier having a non-inverting input for receiving a reference voltage, an inverting input coupled to the second conduction terminal of the power transistor, and an output terminal coupled to a first conduction terminal of a transmission gate having a second conduction terminal coupled to a control terminal of the power transistor and a control terminal for receiving an enable signal; and a slew rate control unit configured to control the slew rate of the driving current.

    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD

    公开(公告)号:US20220308892A1

    公开(公告)日:2022-09-29

    申请号:US17654537

    申请日:2022-03-11

    Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.

    POWER SUPPLY SYSTEM
    9.
    发明申请

    公开(公告)号:US20220271663A1

    公开(公告)日:2022-08-25

    申请号:US17650463

    申请日:2022-02-09

    Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.

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