公开(公告)号：US20230009329A1

公开(公告)日：2023-01-12

申请号：US17850207

申请日：2022-06-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4096

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.

公开(公告)号：US20230008833A1

公开(公告)日：2023-01-12

申请号：US17849903

申请日：2022-06-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

公开(公告)号：US20250069678A1

公开(公告)日：2025-02-27

申请号：US18939751

申请日：2024-11-07

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh CHAWLA ,  Tanuj KUMAR ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/36

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US20230102492A1

公开(公告)日：2023-03-30

申请号：US17954060

申请日：2022-09-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C7/10 ,  G11C7/12

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

公开(公告)号：US20230012303A1

公开(公告)日：2023-01-12

申请号：US17852567

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Harsh RAWAT ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

公开(公告)号：US20230008275A1

公开(公告)日：2023-01-12

申请号：US17844434

申请日：2022-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Nitin CHAWLA ,  Promod KUMAR ,  Manuj AYODHYAWASI ,  Harsh RAWAT

IPC: G11C11/408 ,  G11C11/4076 ,  G11C11/4074 ,  G11C7/04 ,  H03K19/17728

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.

公开(公告)号：US20220122657A1

公开(公告)日：2022-04-21

申请号：US17494683

申请日：2021-10-05

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI

IPC: G11C11/419 ,  G11C11/412

Abstract: An integrated circuit includes a memory array. The memory array includes a plurality of bitlines. The bitlines are each coupled to a respective local I/O circuit. All of the local I/O circuits are coupled to a global I/O circuit. Each local I/O circuit includes a first sensing stage for reading data from the memory cell. The global I/O circuit includes a second sensing stage for reading data from the memory cell.

公开(公告)号：US20210327501A1

公开(公告)日：2021-10-21

申请号：US17221383

申请日：2021-04-02

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI

IPC: G11C11/419 ,  G11C11/412

Abstract: A static random access memory (SRAM) architecture includes a first column of SRAM cells coupled between a first bit line and a first complementary bit line, and first write circuit for the first column. The first write circuit includes a first latch receiving first input data and providing complementary outputs to the first bit line and the first complementary bit line. The first write circuit has a latchable output state driving the first bit line and first complementary bit line, and the latchable output state does not change between consecutive write operations if a state of the received first input data does not change between the consecutive write operations, but does change between the consecutive write operations if the state of the received first input data changes between the consecutive write operations.

公开(公告)号：US20210193669A1

公开(公告)日：2021-06-24

申请号：US17118372

申请日：2020-12-10

Applicant: STMicroelectronics International N.V.

Inventor： Shafquat Jahan AHMED ,  Kedar Janardan DHORI

IPC: H01L27/11

Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.

公开(公告)号：US20210181828A1

公开(公告)日：2021-06-17

申请号：US17111373

申请日：2020-12-03

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Anuj GROVER ,  Giuseppe DESOLI ,  Kedar Janardan DHORI ,  Thomas BOESCH ,  Promod KUMAR

IPC: G06F1/3234 ,  G11C11/413 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/78

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.