公开(公告)号：US07159143B2

公开(公告)日：2007-01-02

申请号：US10766951

申请日：2004-01-30

申请人： Sadami Takeoka ,  Seiji Kajihara

发明人： Sadami Takeoka ,  Seiji Kajihara

IPC分类号： G06F11/00

CPC分类号： G01R31/3016

摘要： All untestable delay faults are hardly calculated. Thus, when the fault coverage of an test sequence for a delay fault is calculated, the fault coverage is not calculated without excluding the number of untestable faults. Accordingly the fault coverage does not correctly represent a test quality.The delay faults are partly selected to analyze how many untestable delay faults exist among the selected delay faults. Thus, the, number of untestable delay faults included all the delay faults are estimated. Thus, a method for evaluating a delay fault test quality for calculating the fault coverage that correctly represents the test quality by using this value is provided.

摘要翻译： 所有不可逾越的延迟故障几乎不计算。 因此，当计算延迟故障的测试序列的故障覆盖时，不计算故障覆盖范围，而不排除不可测故障的数量。 因此，故障覆盖不能正确表示测试质量。 部分选择延迟故障来分析所选延迟故障中存在多少不可测延迟故障。 因此，估计了不可逾越的延迟故障的数量，包括所有的延迟故障。 因此，提供了一种通过使用该值来评估用于计算正确表示测试质量的故障覆盖的延迟故障测试质量的方法。

公开(公告)号：US20070038908A1

公开(公告)日：2007-02-15

申请号：US11378396

申请日：2006-03-20

申请人： Yoko Hirano ,  Katsuya Fujimura ,  Aya Mototani ,  Sadami Takeoka

发明人： Yoko Hirano ,  Katsuya Fujimura ,  Aya Mototani ,  Sadami Takeoka

IPC分类号： G01R31/28

CPC分类号： G01R31/31704 ,  G01R31/31701 ,  G01R31/3172

摘要： Design data including circuit data on a test point and information about a test mode, which has been attached to the test point, is inputted to an apparatus for designing a semiconductor integrated circuit. A design data code analysis unit in a data input unit performs the code analysis of the design data and, after the code analysis, the resulting design data is stored by a database storage unit in a storage device. A test point deletion unit receives the test mode specified from the outside and deletes data on an unnecessary test point from the design data stored in the storage device. The design data which does not include the unnecessary test point is outputted from a data output unit. Accordingly, even when the test mode is changed, there is no need to calculate the test efficiency again in response to each change or add the step of inserting a new test point.

摘要翻译： 包括测试点的电路数据的设计数据和已经附加到测试点的测试模式的信息被输入到用于设计半导体集成电路的设备。 数据输入单元中的设计数据代码分析单元执行设计数据的代码分析，并且在代码分析之后，所得到的设计数据由数据库存储单元存储在存储设备中。 测试点删除单元接收从外部指定的测试模式，并从存储在存储设备中的设计数据中删除不必要的测试点上的数据。 不包括不必要的测试点的设计数据从数据输出单元输出。 因此，即使在变更了测试模式的情况下，也不需要根据每次变更再次计算测试效率，或者添加插入新的测试点的步骤。

公开(公告)号：US06799292B2

公开(公告)日：2004-09-28

申请号：US09799583

申请日：2001-03-07

申请人： Sadami Takeoka ,  Sudhakar M. Reddy ,  Seiji Kajihara

发明人： Sadami Takeoka ,  Sudhakar M. Reddy ,  Seiji Kajihara

IPC分类号： G01R3128

CPC分类号： G01R31/318544 ,  G01R31/318371

摘要： A path under test is selected from a semiconductor integrated circuit that has been designed by a scan method. A test pattern is generated for the selected path so that the path is sensitized and a signal, passing through the path, changes its level at a time before or after a capture clock pulse is input to the circuit. Next, the test pattern generated is transformed into a normal scan pattern. Also, an expected output value, which should result from the test pattern input, is obtained. Then, the test pattern is input to the path under test and the resultant output value is compared to the expected value. In this manner, the path can be tested in such a manner as to see whether or not any hold error will occur.

摘要翻译： 从通过扫描方法设计的半导体集成电路中选择被测路径。 为所选择的路径生成测试图案，使得路径被敏化，并且通过路径的信号在捕获时钟脉冲被输入到电路之前或之后改变其电平。 接下来，将生成的测试图案变换成正常扫描图案。 此外，获得了由测试图案输入产生的预期输出值。 然后，将测试图案输入到测试路径，并将结果输出值与预期值进行比较。 以这种方式，可以以这样的方式测试路径，以确定是否发生任何保持错误。

公开(公告)号：US07475378B2

公开(公告)日：2009-01-06

申请号：US11079292

申请日：2005-03-15

申请人： Sadami Takeoka

发明人： Sadami Takeoka

IPC分类号： G06F17/50

CPC分类号： G01R31/318586

摘要： A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

摘要翻译： 一种设计半导体集成电路的方法包括以下步骤：选择要作为扫描链连接的一对扫描寄存器，并计算硬件上从前级扫描寄存器的每个输出端到扫描数据输入端的扫描数据输入端 后级扫描寄存器。 该方法还包括以下步骤：基于上述计算，在具有最小直线距离的前级选择扫描寄存器的输出端; 确定将所选输出端与后级扫描寄存器的扫描数据输入端连接; 以及通过使用在前一步骤中确定的输出端子连接每对扫描寄存器来形成扫描链。

公开(公告)号：US07017135B2

公开(公告)日：2006-03-21

申请号：US09843687

申请日：2001-04-30

申请人： Sadami Takeoka ,  Takahiro Ichinomiya ,  Akira Motohara

发明人： Sadami Takeoka ,  Takahiro Ichinomiya ,  Akira Motohara

IPC分类号： G06F17/50

CPC分类号： G01R31/318586

摘要： A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

摘要翻译： 一种设计半导体集成电路的方法包括以下步骤：选择要作为扫描链连接的一对扫描寄存器，并计算硬件上从前级扫描寄存器的每个输出端到扫描数据输入端的扫描数据输入端 后级扫描寄存器。 该方法还包括以下步骤：基于上述计算，在具有最小直线距离的前级处选择扫描寄存器的输出端; 确定将所选输出端与后级扫描寄存器的扫描数据输入端连接; 以及通过使用在前一步骤中确定的输出端子连接每对扫描寄存器来形成扫描链。

公开(公告)号：US06282506B1

公开(公告)日：2001-08-28

申请号：US08803145

申请日：1997-02-19

申请人： Sadami Takeoka ,  Takahiro Ichinomiya ,  Akira Motohara

发明人： Sadami Takeoka ,  Takahiro Ichinomiya ,  Akira Motohara

IPC分类号： G06F1127

CPC分类号： G01R31/318586

摘要： A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

摘要翻译： 一种设计半导体集成电路的方法包括以下步骤：选择要作为扫描链连接的一对扫描寄存器，并计算硬件上从前级扫描寄存器的每个输出端到扫描数据输入端的扫描数据输入端 后级扫描寄存器。 该方法还包括以下步骤：基于上述计算，在具有最小直线距离的前级选择扫描寄存器的输出端; 确定将所选输出端与后级扫描寄存器的扫描数据输入端连接; 以及通过使用在前一步骤中确定的输出端子连接每对扫描寄存器来形成扫描链。

公开(公告)号：US20050028051A1

公开(公告)日：2005-02-03

申请号：US10766951

申请日：2004-01-30

申请人： Sadami Takeoka ,  Seiji Kajihara

发明人： Sadami Takeoka ,  Seiji Kajihara

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/3181 ,  G06F17/50 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20

CPC分类号： G01R31/3016

摘要： All untestable delay faults are hardly calculated. Thus, when the fault coverage of an test sequence for a delay fault is calculated, the fault coverage is not calculated without excluding the number of untestable faults. Accordingly the fault coverage does not correctly represent a test quality. The delay faults are partly selected to analyze how many untestable delay faults exist among the selected delay faults. Thus, the, number of untestable delay faults included all the delay faults are estimated. Thus, a method for evaluating a delay fault test quality for calculating the fault coverage that correctly represents the test quality by using this value is provided.

摘要翻译： 所有不可逾越的延迟故障几乎不计算。 因此，当计算延迟故障的测试序列的故障覆盖时，不计算故障覆盖范围，而不排除不可测故障的数量。 因此，故障覆盖不能正确表示测试质量。 部分选择延迟故障来分析所选延迟故障中存在多少不可测延迟故障。 因此，估计了不可逾越的延迟故障的数量，包括所有的延迟故障。 因此，提供了一种通过使用该值来评估用于计算正确表示测试质量的故障覆盖的延迟故障测试质量的方法。

公开(公告)号：US5430736A

公开(公告)日：1995-07-04

申请号：US868737

申请日：1992-04-15

申请人： Sadami Takeoka ,  Akira Motohara

发明人： Sadami Takeoka ,  Akira Motohara

IPC分类号： G01R31/3183 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/263

CPC分类号： G01R31/318586 ,  G01R31/318547 ,  G01R31/318392

摘要： In an apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit wherein logical values of bits of the plurality of storage elements being represented by a state, first external input values are generated so that a transition process is performed from a second state of the plurality of storage elements to a first state thereof, and second external input values are generated so hat a transition process is performed from a third state of the plurality of storage elements to the first state thereof. Thereafter, third external input values are generated so that a transition process is performed from a fourth state of the plurality of storage elements to the first state thereof. After setting the fourth state as the first state, name data of storage elements corresponding to bits of different states between the second and third states are stored in a storage unit. After setting the third state as the first state, there is increased a degree of requesting a scan operation for each of the storage elements, name data of which have been stored in the storage unit. Then, storage elements to be scanned are selected for generating an improved test pattern based on the degree of requesting the scan operation.

摘要翻译： 在用于生成包括多个存储元件的顺序逻辑电路的测试图案的装置中，每个存储元件存储一位的逻辑值，其中多个存储元件的位的逻辑值由状态表示，第一外部输入值 被产生，使得从多个存储元件的第二状态到其第一状态执行转换处理，并且产生第二外部输入值，从而从多个存储元件的第三状态执行转换处理， 其第一个状态。 此后，产生第三外部输入值，使得从多个存储元件的第四状态到其第一状态执行转换处理。 在将第四状态设置为第一状态之后，将与第二状态和第三状态之间的不同状态的位对应的存储元件的名称数据存储在存储单元中。 在将第三状态设置为第一状态之后，对存储单元中已存储的每个存储元件的每个存储元件请求扫描操作的程度增加。 然后，选择要扫描的存储元件，以便基于请求扫描操作的程度产生改进的测试图案。

公开(公告)号：US07613972B2

公开(公告)日：2009-11-03

申请号：US11585778

申请日：2006-10-25

申请人： Sadami Takeoka ,  Shinichi Yoshimura

发明人： Sadami Takeoka ,  Shinichi Yoshimura

IPC分类号： G01R31/28

CPC分类号： G01R31/318552

摘要： A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational circuit section in accordance with a scan enable signal and in synchronization with a clock signal, and a clock control section for generating and outputting a predetermined number of pulses as the clock signal after a predetermined period has passed since a time when an output command signal was received. The clock control section has an oscillator circuit for generating and outputting the pulse, and is configured to output a last pulse of the predetermined number of pulses in a manner which holds a logical value immediately after an active edge for the scan path circuit.

摘要翻译： 半导体集成电路包括具有组合电路的组合电路部分，用于根据扫描使能信号并与时钟信号同步地输入和输出组合电路部分的值的扫描路径电路，以及时钟控制 从接收到输出命令信号的时刻起经过预定​​时间段之后，生成并输出预定数量的脉冲作为时钟信号。 时钟控制部分具有用于产生和输出脉冲的振荡器电路，并且被配置为以保持紧接在扫描路径电路的有效边沿之后的逻辑值的方式输出预定数量的脉冲的最后脉冲。

公开(公告)号：US20070113131A1

公开(公告)日：2007-05-17

申请号：US11585778

申请日：2006-10-25

申请人： Sadami Takeoka ,  Shinichi Yoshimura

发明人： Sadami Takeoka ,  Shinichi Yoshimura

IPC分类号： G01R31/28

CPC分类号： G01R31/318552

摘要： A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational circuit section in accordance with a scan enable signal and in synchronization with a clock signal, and a clock control section for generating and outputting a predetermined number of pulses as the clock signal after a predetermined period has passed since a time when an output command signal was received. The clock control section has an oscillator circuit for generating and outputting the pulse, and is configured to output a last pulse of the predetermined number of pulses in a manner which holds a logical value immediately after an active edge for the scan path circuit.

摘要翻译： 半导体集成电路包括具有组合电路的组合电路部分，用于根据扫描使能信号并与时钟信号同步地输入和输出组合电路部分的值的扫描路径电路，以及时钟控制 从接收到输出命令信号的时刻起经过预定​​时间段之后，生成并输出预定数量的脉冲作为时钟信号。 时钟控制部分具有用于产生和输出脉冲的振荡器电路，并且被配置为以保持紧接在扫描路径电路的有效边沿之后的逻辑值的方式输出预定数量的脉冲的最后脉冲。