公开(公告)号：US20200243374A1

公开(公告)日：2020-07-30

申请号：US16539064

申请日：2019-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hoon CHOI ,  Jaeung KOO ,  Kwansung KIM ,  Bo Yun KIM ,  Wandon KIM ,  Boun YOON ,  Jeonghyuk YIM ,  Yeryung JEON

IPC: H01L21/768 ,  H01L27/105 ,  H01L21/3105 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.

公开(公告)号：US20160027901A1

公开(公告)日：2016-01-28

申请号：US14697829

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine PARK ,  Jae-Jik BAEK ,  Myunggeun SONG ,  Boun YOON ,  Sukhun CHOI ,  Jeongnam HAN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/0228 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode.

Abstract translation: 提供了一种半导体器件，其包括具有活性图案的衬底，与有源图案交叉的栅极电极和栅电极上的栅极覆盖图案。 栅极封盖图案可以具有大于栅电极的宽度的宽度，并且栅极封盖图案可以包括朝向衬底延伸的延伸部分，并且至少部分地覆盖栅电极的两个侧壁。