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    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230253241A1

    公开(公告)日：2023-08-10

    申请号：US17965927

    申请日：2022-10-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youncheol JEONG ,  Jaeung KOO ,  Boun YOON ,  Ilyoung YOON

    IPC: H01L21/762 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238

    CPC classification number: H01L21/76232 ,  H01L27/0924 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/823878 ,  H01L29/7851

    Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode extending in a second direction and crossing the active pattern, a gate capping pattern covering a top surface of the gate electrode, and a separation structure at a side of the gate electrode and extending in the second direction to penetrate the active pattern in a third direction. The first and second directions are parallel to a bottom surface of the substrate and are perpendicular to the third direction. The separation structure may include a filling pattern, which extends in the third direction to penetrate the active pattern, and a vertical insulating pattern, which is interposed between the filling pattern and the gate electrode. A top surface of the separation structure may be located at a height lower than a top surface of the gate capping pattern.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230005935A1

    公开(公告)日：2023-01-05

    申请号：US17713327

    申请日：2022-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee LEE ,  Jonghyuk PARK ,  Ilyoung YOON ,  Boun YOON ,  Jeehwan HEO

    IPC: H01L27/108

    Abstract: A semiconductor device may include a substrate, a patterned structure, a filling pattern, and a conductive spacer. The substrate may include a semiconductor chip region and an overlay region. The patterned structure may include bit line structures spaced by a first distance on the semiconductor region, define a first trench and a second trench on first and second regions of the overlay region, and include key structures on the second region and spaced apart by the second trench. The filling pattern may fill lower portions of the first and second trenches on the first and second regions. The first region may be an edge portion of the overlay region. The second region may be a central portion of the overlay region. The conductive spacer may contact an upper surface of the filling pattern and may be on an upper sidewall of each of the first and second trenches.

    SEMICONDUCTOR DEVICES
    6.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220069101A1

    公开(公告)日：2022-03-03

    申请号：US17196321

    申请日：2021-03-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seunghoon CHOI ,  Ilyoung YOON ,  Ilsu PARK ,  Kiho BAE ,  Boun YOON ,  Yooyong LEE

    IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8234

    Abstract: A semiconductor device including a substrate; a gate structure on the substrate; a gate spacer on a sidewall of the gate structure; and a polishing stop pattern on the gate structure and the gate spacer, the polishing stop pattern including a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and a second portion extending from the first portion in a vertical direction substantially perpendicular to an upper surface of the substrate, wherein an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the first portion thereof, and the upper surface of the central portion of the first portion of the polishing stop pattern is substantially coplanar with an upper surface of the second portion thereof.

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    7.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20180166343A1

    公开(公告)日：2018-06-14

    申请号：US15646300

    申请日：2017-07-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki Ho BAE ,  Jaeseok KIM ,  Hoyoung KIM ,  Boun YOON ,  KyungTae LEE ,  Kwansung KIM ,  Eunji PARK

    IPC: H01L21/8234

    CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823437

    Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.

    SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTION STRUCTURE
    8.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTION STRUCTURE 审中-公开

    公开(公告)号：US20240014068A1

    公开(公告)日：2024-01-11

    申请号：US18217724

    申请日：2023-07-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yanghee LEE ,  Byoungho KWON ,  Jonghyuk PARK ,  Boun YOON ,  Ilyoung YOON ,  Seokjun HONG

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00

    CPC classification number: H01L21/76832 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/53238 ,  H01L21/76816 ,  H01L23/53295 ,  H10B12/315

    Abstract: A semiconductor device includes a lower structure; an intermediate insulating structure on the lower structure; an intermediate interconnection structure penetrating through the intermediate insulating structure; an upper insulating structure on the intermediate insulating structure and the intermediate interconnection structure; and an upper conductive pattern penetrating through the upper insulating structure and electrically connected to the intermediate interconnection structure, wherein the intermediate insulating structure includes an intermediate etch-stop layer and an intermediate insulating layer thereon, the intermediate insulating layer includes first and second intermediate material layers, the second intermediate material layer having an upper surface coplanar with an upper surface of the first intermediate material layer, the intermediate interconnection structure penetrates through the first intermediate material layer and the intermediate etch-stop layer, and a material of the first intermediate material layer has a dielectric constant that is higher than a dielectric constant of a material of the second intermediate material layer.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200185398A1

    公开(公告)日：2020-06-11

    申请号：US16793301

    申请日：2020-02-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Miso SHIN ,  Myeongan KWON ,  Chungki MIN ,  Byoungho KWON ,  Boun YOON

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/11519

    Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

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