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    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    21.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230168819A1

    公开(公告)日：2023-06-01

    申请号：US17842981

    申请日：2022-06-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0626 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068

    Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    24.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11829614B2

    公开(公告)日：2023-11-28

    申请号：US17842981

    申请日：2022-06-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0626 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068

    Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.

    Memory device performing refresh operation and method of operating the same
    26.
    发明授权
    Memory device performing refresh operation and method of operating the same 有权

    公开(公告)号：US11631448B1

    公开(公告)日：2023-04-18

    申请号：US17244466

    申请日：2021-04-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eunae Lee ,  Sunghye Cho ,  Kijun Lee ,  Junjin Kong ,  Yeonggeol Song

    IPC: G11C11/406 ,  G06F12/06

    Abstract: A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

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