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    SEMICONDUCTOR MEMORY DEVICES
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230367672A1

    公开(公告)日：2023-11-16

    申请号：US18226622

    申请日：2023-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

    IPC: G06F11/10

    CPC classification number: G06F11/1068

    Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    3.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230168819A1

    公开(公告)日：2023-06-01

    申请号：US17842981

    申请日：2022-06-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0626 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068

    Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.

    Semiconductor memory device and method of operating the same
    4.
    发明授权
    Semiconductor memory device and method of operating the same 有权

    公开(公告)号：US12288578B2

    公开(公告)日：2025-04-29

    申请号：US17864736

    申请日：2022-07-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Byeonggyu Park ,  Yeonggeol Song

    IPC: G11C11/406 ,  G11C11/4093

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS 有权

    公开(公告)号：US20230119555A1

    公开(公告)日：2023-04-20

    申请号：US17736154

    申请日：2022-05-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sunghye Cho ,  Yeonggeol Song ,  Kijun Lee ,  Myungkyu Lee

    IPC: G06F11/10 ,  G06F11/07 ,  H03M13/11

    Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.

    SEMICONDUCTOR MEMORY DEVICES
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220405165A1

    公开(公告)日：2022-12-22

    申请号：US17535762

    申请日：2021-11-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Sunggi Ahn ,  Yesin Ryu ,  Sukhan Lee

    IPC: G06F11/10 ,  G11C29/04

    Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    8.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11314592B2

    公开(公告)日：2022-04-26

    申请号：US16909730

    申请日：2020-06-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee

    IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4091 ,  G11C11/56 ,  G11C11/4093 ,  H01L25/065

    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t−2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.

    ERROR CORRECTION DEVICE AND METHOD FOR GENERATING SYNDROMES AND PARTIAL COEFFICIENT INFORMATION IN A PARALLEL
    9.
    发明申请
    ERROR CORRECTION DEVICE AND METHOD FOR GENERATING SYNDROMES AND PARTIAL COEFFICIENT INFORMATION IN A PARALLEL 有权

    公开(公告)号：US20210384919A1

    公开(公告)日：2021-12-09

    申请号：US17199803

    申请日：2021-03-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunae Lee ,  Kijun Lee ,  Yeonggeol Song ,  Myungkyu Lee ,  Seokha Hwang

    IPC: H03M13/15 ,  G06F11/10

    Abstract: An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.

    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME
    10.
    发明申请
    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20210194508A1

    公开(公告)日：2021-06-24

    申请号：US16987554

    申请日：2020-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho ,  Chanki Kim ,  Yeonggeol Song

    IPC: H03M13/15 ,  H03M13/11 ,  G06F11/10 ,  G06F9/30

    Abstract: A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

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