公开(公告)号：US11695009B2

公开(公告)日：2023-07-04

申请号：US17195019

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Jongho Lee ,  Geumjong Bae

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L29/417

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78696

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

公开(公告)号：US20220115531A1

公开(公告)日：2022-04-14

申请号：US17556001

申请日：2021-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  Dong IL BAE ,  Geumjong Bae ,  Seungmin Song ,  Junggil Yang

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20210193659A1

公开(公告)日：2021-06-24

申请号：US17195019

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Jongho Lee ,  Geumjong Bae

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L29/417

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

公开(公告)号：US10978486B2

公开(公告)日：2021-04-13

申请号：US16295198

申请日：2019-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun Kim ,  Jaehyeoung Ma ,  Geumjong Bae

IPC: H01L27/118 ,  H01L21/8238

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include first and second active patterns on a substrate. Each of the first and second active patterns may extend in a first direction. The first and second active patterns may be aligned along the first direction and may be separated by a first trench extending in a second direction. The first trench may define a first sidewall of the first active pattern. The semiconductor devices may also include a channel pattern including first and second semiconductor patterns stacked on the first active pattern, a dummy gate electrode on the channel pattern and extending in the second direction, and a gate spacer on one side of the dummy gate electrode, the one side of the dummy gate electrode being adjacent to the first trench. The gate spacer may cover a first sidewall of the first active pattern.