公开(公告)号：US11251312B2

公开(公告)日：2022-02-15

申请号：US16395907

申请日：2019-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mongsong Liang ,  Sung-Dae Suk ,  Geumjong Bae

IPC: H01L29/423 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/11 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

公开(公告)号：US10109631B2

公开(公告)日：2018-10-23

申请号：US15438113

申请日：2017-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Jongho Lee ,  Geumjong Bae

IPC: H01L27/092 ,  H01L23/535 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

公开(公告)号：US11978739B2

公开(公告)日：2024-05-07

申请号：US17199497

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun Kim ,  Jaehyeoung Ma ,  Geumjong Bae

IPC: H01L27/118 ,  H01L29/423

CPC classification number: H01L27/11807 ,  H01L29/42392 ,  H01L2027/11829

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include first and second active patterns on a substrate. Each of the first and second active patterns may extend in a first direction. The first and second active patterns may be aligned along the first direction and may be separated by a first trench extending in a second direction. The first trench may define a first sidewall of the first active pattern. The semiconductor devices may also include a channel pattern including first and second semiconductor patterns stacked on the first active pattern, a dummy gate electrode on the channel pattern and extending in the second direction, and a gate spacer on one side of the dummy gate electrode, the one side of the dummy gate electrode being adjacent to the first trench. The gate spacer may cover a first sidewall of the first active pattern.

公开(公告)号：US10991694B2

公开(公告)日：2021-04-27

申请号：US16137625

申请日：2018-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Jongho Lee ,  Geumjong Bae

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L29/417

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

公开(公告)号：US10749030B2

公开(公告)日：2020-08-18

申请号：US16018121

申请日：2018-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojin Jeong ,  Dong Il Bae ,  Geumjong Bae ,  Seungmin Song ,  Junggil Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US10090328B2

公开(公告)日：2018-10-02

申请号：US15429719

申请日：2017-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil Yang ,  Dong Il Bae ,  Geumjong Bae ,  Seungmin Song ,  Jongho Lee

IPC: H01L23/48 ,  H01L27/12 ,  H01L27/02 ,  H01L29/78

Abstract: A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.

公开(公告)号：US11942558B2

公开(公告)日：2024-03-26

申请号：US17574166

申请日：2022-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mongsong Liang ,  Sung-Dae Suk ,  Geumjong Bae

IPC: H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/78696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/78618 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

公开(公告)号：US11211495B2

公开(公告)日：2021-12-28

申请号：US16922464

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojin Jeong ,  Dong Il Bae ,  Geumjong Bae ,  Seungmin Song ,  Junggil Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US10916658B2

公开(公告)日：2021-02-09

申请号：US16894270

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  Dong Il Bae

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US10714617B2

公开(公告)日：2020-07-14

申请号：US16011785

申请日：2018-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  Dong Il Bae

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.