公开(公告)号：US09502425B2

公开(公告)日：2016-11-22

申请号：US14532152

申请日：2014-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L27/02

CPC classification number: H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 一个半导体器件包括衬底，设置在衬底上的器件隔离层，由器件隔离层限定并且具有高于器件隔离层的顶表面的顶表面的翅片型有源图案，设置在器件隔离层上的第一导电线 翅片型有源图案的边缘部分和与鳍式有源图案的边缘部分相邻的器件隔离层，以及设置在鳍式有源图案和第一导电线之间的绝缘薄层。 第一导线形成可以施加写入电压的反熔丝的栅电极。

公开(公告)号：US09419004B2

公开(公告)日：2016-08-16

申请号：US14575647

申请日：2014-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda

IPC: H01L23/52 ,  H01L27/112 ,  H01L23/525 ,  H01L29/78 ,  H01L27/06

CPC classification number: H01L27/11206 ,  H01L23/5256 ,  H01L27/0629 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse structure includes a first fin pattern disposed in a field insulating layer that includes an upper surface that projects above an upper surface of the field insulating layer, a conductive pattern on the field insulating layer that crosses the first fin pattern, a first semiconductor region positioned on at least one side of the conductive pattern, and first and second contacts disposed on the conductive pattern on each side of the first fin pattern. The fuse structure may be included in a semiconductor device.

Abstract translation: 熔丝结构包括：设置在场绝缘层中的第一鳍状图案，其包括突出在所述场绝缘层的上表面上方的上表面;所述场绝缘层上穿过所述第一鳍状图案的导电图案;第一半导体区域 位于导电图案的至少一侧，以及设置在第一鳍片图案的每一侧上的导电图案上的第一和第二触点。 熔丝结构可以包括在半导体器件中。

公开(公告)号：US09368445B2

公开(公告)日：2016-06-14

申请号：US14814049

申请日：2015-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda

IPC: H01L23/525 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material.

公开(公告)号：US09230925B2

公开(公告)日：2016-01-05

申请号：US14261505

申请日：2014-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda

IPC: H01L23/52 ,  H01L23/62 ,  H01L21/768 ,  H01L23/498 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/62 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.

Abstract translation: 提供熔丝结构及其吹塑方法。 熔丝结构包括在基板上的导电线，导电线上彼此间隔开的第一和第二通孔，电连接到第一通孔的阴极电极线，电连接到第一通孔的阳极电极线 第二通孔和与阴极和阳极电极线中的至少一个相邻并且与导电线电绝缘的虚设图案。

公开(公告)号：US09087842B2

公开(公告)日：2015-07-21

申请号：US14304750

申请日：2014-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Ji-Hoon Yoon ,  Sung-Man Lim

IPC: H01L27/10 ,  H01L29/00 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via.

Abstract translation: 半导体器件包括具有熔丝区域和器件区域的衬底; 保险丝区域的绝缘层中的熔丝结构，以及设备区域的绝缘层中的线结构。 熔丝结构包括熔丝通孔，熔丝线与熔丝通孔图案的顶端电连接并沿一个方向延伸。 导线结构包括导线通孔，电线连接到导线通孔的顶端并沿第一方向延伸的导线。 保险丝通孔的第一方向上的宽度小于电线通路的第一方向上的宽度。