公开(公告)号：US09646711B2

公开(公告)日：2017-05-09

申请号：US14676819

申请日：2015-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda

IPC: G11C5/02 ,  G11C17/16 ,  H01L23/525 ,  H01L27/112

CPC classification number: G11C17/16 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes first through fourth active regions arranged sequentially along a first direction, and which extend along a second direction different from the first direction; a first gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, and extending along the first direction; a second gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, extending along the second direction, and arranged so that no other gate electrodes are between the first gate electrode and the second gate electrode in the second direction; the first gate electrode extending between a first end and a second end;a first wiring line which is formed on the first gate electrode; a first strap contact, which connects the first wiring line and the first gate electrode between the first active region and the second active region; and a second strap contact, which connects the first wiring line and the first gate electrode between the third active region and the fourth active region.

公开(公告)号：US09336894B2

公开(公告)日：2016-05-10

申请号：US14753620

申请日：2015-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Ji-Hoon Yoon

IPC: G11C17/00 ,  G11C17/08 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C11/5685 ,  G11C11/5692 ,  G11C13/0007 ,  G11C13/0069 ,  G11C17/165 ,  G11C17/18 ,  G11C2213/53

Abstract: A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.

Abstract translation: 存储器件可以包括非易失性存储器单元。 非易失性存储器单元的第一存储单元可以具有第一状态的第一电阻值，并且非易失性存储单元的第二存储单元可具有小于第二状态的第一电阻值的第二电阻值。 非易失性存储单元的第三存储单元可具有小于第一电阻值的第三电阻值并且大于第三状态中的第二电阻值，并且非易失性存储单元的第四存储单元可具有较小的第四电阻值 大于第四电阻值且大于第四电阻值。

公开(公告)号：US20150076655A1

公开(公告)日：2015-03-19

申请号：US14261505

申请日：2014-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu MAEDA

IPC: H01L23/62 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/62 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.

Abstract translation: 提供熔丝结构及其吹塑方法。 熔丝结构包括在基板上的导电线，导电线上彼此间隔开的第一和第二通孔，电连接到第一通孔的阴极电极线，电连接到第一通孔的阳极电极线 第二通孔和与阴极和阳极电极线中的至少一个相邻并且与导电线电绝缘的虚设图案。

公开(公告)号：US20180197817A1

公开(公告)日：2018-07-12

申请号：US15914142

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5256 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53233 ,  H01L23/53257

Abstract: An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion. A first distance between the first portion and the second portion may be greater than a width of the second portion in a second direction perpendicular to the first direction.

公开(公告)号：US09887202B2

公开(公告)日：2018-02-06

申请号：US15334411

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC: H01L29/78 ,  H01L27/112 ,  H01L29/06 ,  H01L29/423 ,  H01L23/522 ,  H01L23/525 ,  H01L27/02

CPC classification number: H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

公开(公告)号：US09627390B2

公开(公告)日：2017-04-18

申请号：US14683151

申请日：2015-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Ji-Hoon Yoon

IPC: H01L27/112 ,  G11C17/16 ,  H01L23/525

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.

公开(公告)号：US10148811B2

公开(公告)日：2018-12-04

申请号：US15362150

申请日：2016-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gang-Youl Kim ,  Jun-Tai Kim ,  Min-Ho Bae ,  Beak-Kwon Son ,  Jung-Yeol An ,  Chul-Min Choi ,  Yang-Su Kim ,  Jae-Mo Yang ,  Nam-Woog Lee ,  Keun-Won Jang ,  Hyun-Min Choi

IPC: H04M3/00 ,  H04M9/08 ,  G10L21/0208 ,  H04B3/23 ,  G10L21/0216

Abstract: A method, device, a non-transitory computer-readable recording medium for controlling a voice signal by an electronic device including a first microphone, a second microphone, a communication interface, and a processor are provided. The method includes acquiring a first voice signal by using the first microphone; acquiring a second voice signal by using the second microphone; confirming a telephone call mode for performing, by the electronic device, a telephone call with an external electronic device; adjusting a first output attribute corresponding to the first voice signal or a second output attribute corresponding to the second voice signal, based on the telephone call mode; and transmitting the adjusted first voice signal or the adjusted second voice signal to the external electronic device by using the communication interface.

公开(公告)号：US09953919B2

公开(公告)日：2018-04-24

申请号：US15228498

申请日：2016-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi

IPC: H01L23/525 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53233 ,  H01L23/53257

Abstract: An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion. A first distance between the first portion and the second portion may be greater than a width of the second portion in a second direction perpendicular to the first direction.

公开(公告)号：US09935049B2

公开(公告)日：2018-04-03

申请号：US15598627

申请日：2017-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi

IPC: H01L23/525 ,  H01L23/528 ,  H01L23/522 ,  H01L27/112

CPC classification number: H01L23/5256 ,  G11C29/785 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level.

公开(公告)号：US09627314B2

公开(公告)日：2017-04-18

申请号：US14986872

申请日：2016-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda

IPC: H01L23/525 ,  H01L23/62 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/62 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.