公开(公告)号：US11804477B2

公开(公告)日：2023-10-31

申请号：US17371834

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyun Lee ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16155 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L2924/186

Abstract: A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.

公开(公告)号：US11798889B2

公开(公告)日：2023-10-24

申请号：US17835768

申请日：2022-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jongbo Shim ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14

CPC classification number: H01L23/5384 ,  H01L23/14 ,  H01L23/31 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

公开(公告)号：US20220181309A1

公开(公告)日：2022-06-09

申请号：US17371834

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyun Lee ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.

公开(公告)号：US20210183777A1

公开(公告)日：2021-06-17

申请号：US17090502

申请日：2020-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin Yim ,  Jungwoo KIM ,  Jihwang Kim ,  Jongbo Shim ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/14 ,  H01L23/31

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.