公开(公告)号：US20240355796A1

公开(公告)日：2024-10-24

申请号：US18761580

申请日：2024-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAEHO LEE ,  JINHYUN KIM ,  WANSOO PARK

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip disposed on the first redistribution substrate, a first mold layer that covers the first semiconductor chip and the first redistribution substrate, a second redistribution substrate disposed on the first mold layer, a second semiconductor chip disposed on the second redistribution substrate, where the second semiconductor chip includes a second-chip first conductive bump that does not overlap the first semiconductor chip, a first sidewall that overlaps the first semiconductor chip, and a second sidewall that does not overlap the first semiconductor chip, wherein the first sidewall and the second sidewall are opposite to each other, and a first mold via that penetrates the first mold layer connects the second-chip first conductive bump to the first redistribution substrate, and overlaps the second-chip first conductive bump.

公开(公告)号：US20240355746A1

公开(公告)日：2024-10-24

申请号：US18761884

申请日：2024-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chieh-Yen Chen ,  Chuei-Tang Wang ,  Chung-Hao Tsai

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/818 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/182

Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

公开(公告)号：US20240355722A1

公开(公告)日：2024-10-24

申请号：US18761561

申请日：2024-07-02

Applicant: BroadPak Corporation

Inventor： Farhang YAZDANI

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L23/04 ,  H01L23/31 ,  H01L23/473 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/52 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/473 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/573 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L24/80 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/80203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/30107 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183

Abstract: Methods of forming secured substrates are presented. These methods involve creating signal-blocking vias and a series of meshes on various layers of an electronic substrate to mask signal traces and prevent tampering. By strategically positioning ground and power meshes on different layers, and optionally including dummy meshes, the method significantly increases the privacy and security of the electronic substrate. These techniques can also be applied inside or on integrated circuits to enhance security.

公开(公告)号：US20240347439A1

公开(公告)日：2024-10-17

申请号：US18753091

申请日：2024-06-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shin-Puu JENG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Techi WONG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/053 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311

Abstract: A chip package is provided. The chip package includes a substrate structure including: a redistribution structure having a conductive pad; and an insulating layer under the redistribution structure. The chip package includes a first chip over the redistribution structure. The chip package includes a second chip under the substrate structure. A top portion of the second chip extends into the insulating layer from a bottom surface of the insulating layer, the bottom surface faces away from the first chip, and a portion of the insulating layer is between the second chip and the redistribution structure. The chip package includes a first molding layer over the redistribution structure and the first chip. A first sidewall of the first molding layer and a second sidewall of the redistribution structure are substantially level with each other.

公开(公告)号：US12068231B2

公开(公告)日：2024-08-20

申请号：US17688747

申请日：2022-03-07

Applicant: BroadPak Corporation

Inventor： Farhang Yazdani

IPC: H05K1/02 ,  H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L23/04 ,  H01L23/31 ,  H01L23/473 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/52 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/473 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/573 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L24/80 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/80203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/30107 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183

Abstract: Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with cavities formed into the top and/or bottom. The cavities may then be used as locations for the electronic components. Alternatively, narrow spacer interposers may be used to space apart standard more laterally elongated interposers to form the indentations used to house the electronic components. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.

公开(公告)号：US20240258243A1

公开(公告)日：2024-08-01

申请号：US18614579

申请日：2024-03-22

Applicant: Micron Technology, Inc.

Inventor： Jong Sik Paek

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5386 ,  H01L21/4846 ,  H01L21/566 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48228 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/1436 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/183

Abstract: Stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. In some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. Further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. The dielectric structure includes openings corresponding to the bond pads. The module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. The semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.

公开(公告)号：US12051616B2

公开(公告)日：2024-07-30

申请号：US18298780

申请日：2023-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Der-Chyang Yeh

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/10 ,  H01L25/11 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L21/768 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/105 ,  H01L25/115 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/13099 ,  H01L2224/14135 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/429 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2203/1316

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

公开(公告)号：US20240234286A9

公开(公告)日：2024-07-11

申请号：US18340193

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49833 ,  H01L25/105 ,  H10B80/00 ,  H01L24/16 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package including: a front redistribution structure including an insulating layer defining an upper surface, a lower surface opposing the upper surface, and a side surface, front redistribution layers including a first redistribution layer on a first level adjacent to the lower surface and second redistribution layers on a second level higher than the first level relative to the lower surface, the second redistribution layers having an inner redistribution layer and an outer redistribution layer, a recess exposing at least a portion of the outer redistribution layer, and a dam on at least one side of the recess; connection bumps including a first bump electrically connected to the first redistribution layer and a second bump electrically connected to the outer redistribution layer within the recess; and an underfill that extends along a side surface of the second bump and a side surface of the dam within the recess.

公开(公告)号：US12033991B2

公开(公告)日：2024-07-09

申请号：US18086727

申请日：2022-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tong-suk Kim ,  Byeong-yeon Cho

IPC: H01L25/10 ,  G11C5/02 ,  G11C5/04 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  G11C5/025 ,  G11C5/04 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/00014

Abstract: A package-on-package (PoP) semiconductor package includes an upper package and a lower package. The lower package includes a first semiconductor device in a first area, a second semiconductor device in a second area, and a command-and-address vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area.

公开(公告)号：US12033929B2

公开(公告)日：2024-07-09

申请号：US17493352

申请日：2021-10-04

Applicant: Lodestar Licensing Group LLC

Inventor： Owen R. Fay ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/31

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/1413 ,  H01L2224/14179 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/48145 ,  H01L2924/00012

Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.